Abstract: An interconnect structure includes a plurality of first pads arranged to form a first array and a plurality of second pads arranged to form a second array. Each of the first array has a first row, a second row and an mth row extending along a first direction and parallel to each other along a second direction. The first pads in each of the first row, the second row and the mth row are grouped into a first group, a second group and an nth group extending along the second direction. The second pads in each of the first row, the second row and the mth row are grouped into a first group, a second group and an nth group extending along the second direction. The interconnect structure further includes a plurality of first conductive lines, a plurality of second conductive lines and a plurality of nth conductive lines.

Abstract: An auxiliary screening system and an auxiliary screening method for a hip joint of a baby are provided. The auxiliary screening method includes: collecting plural images of the hip joint; performing an image analysis operation on each of the images of the hip joint to extract plural image features of each of the images of the hip joint and determining whether each of the images of the hip joint is a standard image according to the image features of each of the images of the hip joint; and when at least one of the images of the hip joint is determined as the standard image, plural angle parameters are calculated and the at least one of the images of the hip joint that is determined as the standard image is outputted, in which the angle parameters include values of an angle ? and an angle ?.

Abstract: A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.

Abstract: A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.

Abstract: A 3D IC package is provided. The 3D IC package includes: a first IC die comprising a first substrate at a back side of the first IC die; a second IC die stacked at the back side of the first IC die and facing the first substrate; a TSV through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV; and a protection module fabricated in the first substrate, wherein the protection module is electrically connected to the TSV, and the protection module is within the TSV cell.

Abstract: A semiconductor device is disclosed herein. The semiconductor device includes a routing structure. The routing structure has an intermediate conductive routing layer. The intermediate conductive routing layer includes a first mesh conductive layer formed in a predetermined second region of the semiconductor device and a second mesh conductive layer formed in a predetermined first region of the semiconductor device. The first mesh conductive layer and the second mesh conductive layer are electrically isolated from each other. The intermediate conductive routing layer further includes multiple first conductive islands formed in the predetermined first region and multiple second conductive islands formed in the predetermined second region.

Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

Abstract: The present invention provides a transmitter including a mixer, a harmonic impedance adjustment circuit and an amplifier. The mixer is configured to mix a first baseband signal with a first oscillation signal to generate a first mixed signal to a first node, and to mix a second baseband signal with a second oscillation signal to generate a second mixed signal to a second node. The harmonic impedance adjustment circuit is coupled between the first node and the second node, and is configured to reduce harmonic components of the first mixed signal and the second mixed signal to generate an adjusted first mixed signal and an adjusted second mixed signal. The amplifier is coupled to the harmonic impedance adjustment circuit, and is configured to generate an amplified signal according to the adjusted first mixed signal and the adjusted second mixed signal.

Abstract: A semiconductor device includes first and second active regions extending in parallel in a substrate, a plurality of conductive patterns, each conductive pattern of the plurality of conductive patterns extending on the substrate across each of the first and second active regions, and a plurality of metal lines, each metal line of the plurality of metal lines overlying and extending across each of the first and second active regions. Each conductive pattern of the plurality of conductive patterns is electrically connected in parallel with each metal line of the plurality of metal lines.

Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

Abstract: An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.

Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

Abstract: A three dimensional Integrated Circuit (IC) Power Grid (PG) may be provided. The three dimensional IC PG may comprise a first IC die, a second IC die, an interface, and a power distribution structure. The interface may be disposed between the first IC die and the second IC die. The power distribution structure may be connected to the interface. The power distribution structure may comprise at least one Through-Silicon Vias (TSV) and a ladder structure connected to at least one TSV.

Abstract: Packaged semiconductor devices including high-thermal conductivity molding compounds and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution structure; a first die over and electrically coupled to the first redistribution structure; a first through via over and electrically coupled to the first redistribution structure; an insulation layer extending along the first redistribution structure, the first die, and the first through via; and an encapsulant over the insulation layer, the encapsulant surrounding portions of the first through via and the first die, the encapsulant including conductive fillers at a concentration ranging from 70% to about 95% by volume.

Abstract: A beam splitting and combining device includes a first prism, a second prism and a first optical film. The first prism includes a first surface, a second surface and a third surface. The second prism includes a fourth surface, a fifth surface and a sixth surface. The fifth surface and the second surface are attached to each other. The first optical film is formed between the second surface and the fifth surface by coating. A beam in a first range of wavelengths is configured to pass through the first surface, the second surface, the first optical film, the fifth surface and the sixth surface in order or in reverse order, or is configured to pass through the first surface and the third surface in order or in reverse order.

Abstract: A beam splitting and combining device includes a first prism, a second prism and a first optical film. The first prism includes a first surface, a second surface and a third surface. The second prism includes a fourth surface, a fifth surface and a sixth surface. The fifth surface and the second surface are attached to each other. The first optical film is formed between the second surface and the fifth surface by coating. A beam in a first range of wavelengths is configured to pass through the first surface, the second surface, the first optical film, the fifth surface and the sixth surface in order or in reverse order, or is configured to pass through the first surface and the third surface in order or in reverse order.

Abstract: A method for optimizing occlusion occurring in an augmented reality system comprising a depth camera and a two-dimensional camera comprises the steps of: capturing, by a depth camera, a scene and an object in the scene to obtain initial depth data, and capturing, by the two-dimensional camera, the scene and the object to obtain two-dimensional image data; in-painting the initial depth data to obtain in-painted depth data; performing a depth buffer calculation according to the in-painted depth data and a virtual model to obtain an occlusion relationship between the object and the virtual model, and generating an occluded partial image according to the two-dimensional image data and the virtual model; estimating partially approximated polygon according to the occluded partial image; and generating an occluded result according to the partially approximated polygon, the two-dimensional image data and the virtual model.

Abstract: The invention provides an apparatus for fabricating a periodic micro-pattern by laser beams. The apparatus includes an ultrafast laser light source configured to generate an output laser beam. A diffraction optical element is configured to divide the output laser beam into a plurality of diffractive laser beams. A confocal system is configured to focus the plurality of diffractive laser beams on a focal point, so that the plurality of diffractive laser beams produces an interference light beam with interference phenomena. The interference light beam ablates a surface of an element to fabricate a periodic micro-pattern on the surface of the element. The confocal system includes a first lens, a second lens and a light shielding mask. The plurality of diffractive laser beams passes through the first lens, the light shielding mask and the second lens in sequence.

Abstract: A method for optimizing occlusion occurring in an augmented reality system comprising a depth camera and a two-dimensional camera comprises the steps of: capturing, by a depth camera, a scene and an object in the scene to obtain initial depth data, and capturing, by the two-dimensional camera, the scene and the object to obtain two-dimensional image data; in-painting the initial depth data to obtain in-painted depth data; performing a depth buffer calculation according to the in-painted depth data and a virtual model to obtain an occlusion relationship between the object and the virtual model, and generating an occluded partial image according to the two-dimensional image data and the virtual model; estimating partially approximated polygon according to the occluded partial image; and generating an occluded result according to the partially approximated polygon, the two-dimensional image data and the virtual model.

Abstract: The invention provides an apparatus for fabricating a periodic micro-pattern by laser beams. The apparatus includes an ultrafast laser light source configured to generate an output laser beam. A diffraction optical element is configured to divide the output laser beam into a plurality of diffractive laser beams. A confocal system is configured to focus the plurality of diffractive laser beams on a focal point, so that the plurality of diffractive laser beams produces an interference light beam with interference phenomena. The interference light beam ablates a surface of an element to fabricate a periodic micro-pattern on the surface of the element. The confocal system includes a first lens, a second lens and a light shielding mask. The plurality of diffractive laser beams passes through the first lens, the light shielding mask and the second lens in sequence.