Patents by Inventor Poi Siong Teo

Poi Siong Teo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100170086
    Abstract: A magnetically-assisted chip assembly unit for assembling at least one chip having a mounting surface and an attachment surface, wherein the attachment surface supports a magnetisable layer thereon and opposes said mounting surface, onto a substrate that has a corresponding chip mounting surface. The unit comprises a template wafer having at least one recess adapted to accommodate therein said chip; and a master wafer having at least one magnetisable element; wherein the template wafer is mounted on the master wafer and said magnetisable element is located at least proximate to the at least one recess such that the magnetisable element is capable of manipulating the chip into the recess, via its magnetisable layer when the magnetisable element is magnetized and generates a magnetic field. Once in the recess, the attachment surface of the chip faces at least a portion of the recess and the mounting surface of the chip faces an opening of the recess.
    Type: Application
    Filed: November 3, 2006
    Publication date: July 8, 2010
    Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventors: Qasem Ramadan, Seung Uk Yoon, Vaidyanathan Kripesh, Poi Siong Teo, Mahadevan Krishna Iyer
  • Patent number: 6890795
    Abstract: We disclose a technique to generate stretched solder columns (bumps) at the wafer level, suitable for wafer level packaging. This is accomplished through use of using two wafers—the standard (functional) wafer that contains the integrated circuits and a master (dummy) wafer on whose surface is provided an array of solder bumps that is the mirror image of that on the functional wafer. After suitable alignment, both sets of solder bumps are melted and then slowly brought together till they merge. Then, as they cool, they are slowly pulled apart thereby stretching the merged solder columns. Once the latter have fully solidified, they are separated from the master wafer only.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: May 10, 2005
    Assignees: Agency for Science, Technology and Research, National University of Singapore, Georgia Tech Research Corporation
    Inventors: Ee Hua Wong, Ranjan Rajoo, Poi Siong Teo