Patents by Inventor Pong-Hsiung Leu

Pong-Hsiung Leu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6953608
    Abstract: A HDP CVD process for depositing a USG liner followed by a FSG dielectric layer on a metal line pattern is described. The substrate is heated in a chamber with a plasma comprised of Ar and O2. A USG liner is deposited in two steps wherein the first step is without an RF bias and the second step is with a moderate RF bias that does not damage the metal lines or an anti-reflective coating on the metal. The moderate RF bias is critical in forming a sputtering component that redeposits USG to form more uniform sidewalls and better coverage at top corners of metal lines. The USG deposition process has a good gap filling capability and significantly reduces device failure rate by preventing corrosion of metal lines during subsequent thermal process cycles. The method also includes a PECVD deposited FSG layer that is planarized to complete an IMD layer.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: October 11, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pong-Hsiung Leu, Yu-Min Chang, Fang-Wen Tsai, Jo-Wei Chen, Wan-Cheng Yang, Chyi-Tsong Ni
  • Publication number: 20040213921
    Abstract: A HDP CVD process for depositing a USG liner followed by a FSG dielectric layer on a metal line pattern is described. The substrate is heated in a chamber with a plasma comprised of Ar and O2. A USG liner is deposited in two steps wherein the first step is without an RF bias and the second step is with a moderate RF bias that does not damage the metal lines or an anti-reflective coating on the metal. The moderate RF bias is critical in forming a sputtering component that redeposits USG to form more uniform sidewalls and better coverage at top corners of metal lines. The USG deposition process has a good gap filling capability and significantly reduces device failure rate by preventing corrosion of metal lines during subsequent thermal process cycles. The method also includes a PECVD deposited FSG layer that is planarized to complete an IMD layer.
    Type: Application
    Filed: April 23, 2003
    Publication date: October 28, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co.
    Inventors: Pong-Hsiung Leu, Yu-Min Chang, Fang-Wen Tsai, Jo-Wei Chen, Wan-Cheng Yang, Chyi-Tsong Ni