Patents by Inventor Pouya Hashemi

Pouya Hashemi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming a vertical transistor pass gate device
    Patent number: 10930779
    Abstract: A semiconductor device including a fin structure present on a supporting substrate to provide a vertically orientated channel region. A first source/drain region having a first epitaxial material with a diamond shaped geometry is present at first end of the fin structure that is present on the supporting substrate. A second source/drain region having a second epitaxial material with said diamond shaped geometry that is present at the second end of the fin structure. A same geometry for the first and second epitaxial material of the first and second source/drain regions provides a symmetrical device.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: February 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Multiple work function nanosheet field effect transistor using sacrificial silicon germanium growth
    Patent number: 10930762
    Abstract: A method of forming a semiconductor device that includes forming a stack of nanosheets composed of a semiconductor material; and forming a sacrificial layer of a work function adjusting material on the semiconductor material of the stack of nanosheets. In a following step, the work function adjusting material is mixed into the semiconductor material on at least a channel surface of nanosheets. The sacrificial layer is removed. An interfacial oxide layer is formed including elements from the semiconductor material and the work function adjusting layer on said at least the channel surface of the stack of nanosheets. A gate structure including a gate dielectric is formed on the interfacial oxide that is present on the channel surface of the nanosheets.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: February 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Choonghyun Lee, Pouya Hashemi
  • Co-integration of high carrier mobility PFET and NFET devices on the same substrate using low temperature condensation
    Patent number: 10923403
    Abstract: Embodiments of the invention are directed to fin-based field effect transistor (FET) devices formed on a substrate. In a non-limiting example, the devices a first fin formed in a p-type FET (PFET) region of the substrate, wherein the first fin includes a top region, a central region, and a bottom region. The central region of the first fin includes an epitaxial first material in-situ doped with a first type of semiconductor material at a first concentration level. The top region of the first fin includes the epitaxial first material in-situ doped with the first type of semiconductor material at the first concentration level, along with an anneal-induced second concentration level of the first type of semiconductor material. A final concentration level of the first type of semiconductor material in the top region includes the first concentration level and the second concentration level.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: February 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee
  • MRAM STRUCTURE WITH T-SHAPED BOTTOM ELECTRODE TO OVERCOME GALVANIC EFFECT
    Publication number: 20210043827
    Abstract: A memory structure is provided that avoids high resistance due to the galvanic effect. The high resistance is reduced and/or eliminated by providing a T-shaped bottom electrode structure of uniform construction (i.e., a single piece). The T-shaped bottom electrode structure includes a narrow base portion and a wider shelf portion. The shelf portion of the T-shaped bottom electrode structure has a planar topmost surface in which a MTJ pillar forms an interface with.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Pouya Hashemi, Bruce B. Doris, Eugene J. O'Sullivan, Michael F. Lofaro
  • Asymmetric threshold voltage FinFET device by partial channel doping variation
    Patent number: 10916659
    Abstract: A FinFET having an asymmetric threshold voltage distribution is provided by forming a halo ion implantation region in a semiconductor fin, and in close proximity to a source region, of the FinFET. The halo ion implantation region is self-aligned to an outermost sidewall surface of the functional gate structure of the FinFET and it has a higher dopant concentration than the remaining portion of the channel region.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: February 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Choonghyun Lee, Pouya Hashemi, Takashi Ando, Jingyun Zhang
  • Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device
    Patent number: 10916432
    Abstract: Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial layer of a metal gate structure formed on a SiGe channel layer of the FET device. For example, a method comprises growing a first silicon oxide layer on a surface of a SiGe layer using a first oxynitridation process, wherein the first silicon oxide layer comprises nitrogen. The first silicon oxide layer is removed, and a second silicon oxide layer is grown on the surface of the SiGe layer using a second oxynitridation process, which is substantially the same as the first oxynitridation process, wherein the second silicon oxide layer is substantially devoid of germanium oxide and nitrogen. For example, the first silicon oxide layer comprises a SiON layer and the second silicon oxide layer comprises a pure silicon dioxide layer.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: February 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Pouya Hashemi, Hemanth Jagannathan, ChoongHyun Lee, Vijay Narayanan
  • MTJ containing device with replacement top electrode
    Patent number: 10903417
    Abstract: A method of forming a magnetic tunnel junction (MTJ) containing device is provided in which a patterned sacrificial material is present atop a MTJ pillar that is located on a bottom electrode. A passivation material liner and a dielectric material portion laterally surround the MTJ pillar and the patterned sacrificial material. The patterned sacrificial material is removed from above the MTJ pillar and replaced with a top electrode. A seam is present in the top electrode. The method mitigates the possibility of depositing resputtered conductive metal particles on a sidewall of the MTJ pillar. Thus, improved device performance, in terms of a reduction in failure mode, can be obtained.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Alexander Reznicek, Nathan P. Marchack, Bruce B. Doris
  • Sub-fin doped bulk fin field effect transistor (FinFET), Integrated Circuit (IC) and method of manufacture
    Patent number: 10903210
    Abstract: A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the IC. Fins on pedestals are defined, e.g., with a hard mask, in a fin layer on a semiconductor wafer and spaces between the pedestals are filled with dielectric material, e.g., shallow trench isolation (STI). Sacrificial sidewalls are formed along the sides of fins and pedestal sub-fins sidewalls are re-exposed. Pedestal sub-fins are doped with a punch-though dopant and punch-though dopant is diffused into the sub-fins and the bottoms of fins. After removing the hard mask and sacrificial sidewalls, metal FET gates are formed on the fins.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Formation of wrap-around-contact to reduce contact resistivity
    Patent number: 10896965
    Abstract: A method of forming a source/drain contact is provided. The method includes forming a sacrificial layer on a source/drain, and depositing an oxidation layer on the sacrificial layer. The method further includes heat treating the oxidation layer and the sacrificial layer to form a modified sacrificial layer. The method further includes forming a protective liner on the modified sacrificial layer, and depositing an interlayer dielectric layer on the protective liner. The method further includes forming a trench in the interlayer dielectric layer that exposes a portion of the protective liner.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: January 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Adra Carr, Jingyun Zhang, Choonghyun Lee, Takashi Ando, Pouya Hashemi
  • Asymmetric threshold voltages in semiconductor devices
    Patent number: 10896962
    Abstract: Semiconductor devices and methods of forming the same include forming an inner spacer on a semiconductor fin. Two outer spacers are formed around the inner spacer, with one outer spacer being in contact with the inner spacer and with the other outer spacer being separated from the inner spacer by a gap. A dipole-forming layer is formed on the semiconductor fin in the gap. The inner spacer is etched away. A gate stack is formed on the semiconductor fin, between the outer spacers.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: January 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Alexander Reznicek, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi
  • Structured bottom electrode for MTJ containing devices
    Patent number: 10892403
    Abstract: A bottom electrode structure for a magnetic tunnel junction (MTJ) containing device is provided. The bottom electrode structure includes a mesa portion that is laterally surrounded by a recessed region. The recessed region of the bottom electrode structure is laterally adjacent to a dielectric material, and a MTJ pillar is located on the mesa portion of the bottom electrode structure. Such a configuration shields the recessed region from impinging ions thus preventing deposition of resputtered conductive metal particles from the bottom electrode onto the MTJ pillar.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: January 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Nathan P. Marchack, Bruce B. Doris, Pouya Hashemi
  • Formation of self-limited inner spacer for gate-all-around nanosheet FET
    Patent number: 10886369
    Abstract: A semiconductor structure containing a gate-all-around nanosheet field effect transistor having a self-limited inner spacer composed of a rare earth doped germanium dioxide that provides source/drain isolation between rare earth metal silicide ohmic contacts is provided.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jingyun Zhang, Takashi Ando, Choonghyun Lee, Alexander Reznicek, Pouya Hashemi
  • Formation of wrap-around-contact to reduce contact resistivity
    Patent number: 10886376
    Abstract: A method of forming a source/drain contact is provided. The method includes forming a sacrificial layer on a source/drain, and depositing an oxidation layer on the sacrificial layer. The method further includes heat treating the oxidation layer and the sacrificial layer to form a modified sacrificial layer. The method further includes forming a protective liner on the modified sacrificial layer, and depositing an interlayer dielectric layer on the protective liner. The method further includes forming a trench in the interlayer dielectric layer that exposes a portion of the protective liner.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Adra Carr, Jingyun Zhang, Choonghyun Lee, Takashi Ando, Pouya Hashemi
  • Vertically stacked nFETs and pFETs with gate-all-around structure
    Patent number: 10879352
    Abstract: A semiconductor structure including vertically stacked n-type field effect transistors (nFETs) and p-type field effect transistors (pFETs) containing suspended semiconductor channel material nanosheets having an isolation layer located between a pFET source/drain (S/D) structure and an nFET S/D region is provided together with a method of forming such a structure. The pFET S/D structure includes a pFET S/D SiGe region having a first germanium content and an overlying SiGe region having a second germanium content that is greater than the first germanium content.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: December 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jingyun Zhang, Takashi Ando, Pouya Hashemi, Choonghyun Lee, Alexander Reznicek
  • Vertical transport Fin field effect transistors combined with resistive memory structures
    Patent number: 10879311
    Abstract: A resistive memory structure is provided. The resistive memory structure includes a vertical fin on a substrate, wherein the sidewalls of the vertical fin each have a {100} crystal face. The resistive memory structure further includes a fin template on the vertical fin, and a gate structure on the vertical fin. The resistive memory structure further includes a top source/drain on opposite sidewalls of the vertical fin, and a bottom electrode layer on the top source/drain, wherein the bottom electrode layer is on opposite sides of the fin template. The resistive memory structure further includes a first middle resistive layer on a portion of the bottom electrode layer, a top electrode layer on the first middle resistive layer, and a first electrical contact on a portion of the bottom electrode layer.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: December 29, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Choonghyun Lee, Takashi Ando, Alexander Reznicek, Jingyun Zhang, Pouya Hashemi
  • VERTICAL FET WITH ASYMMETRIC THRESHOLD VOLTAGE AND CHANNEL THICKNESSES
    Publication number: 20200403065
    Abstract: An FET comprises a source, a drain, a channel, and a gate encompassing the channel. The channel has a first region that is thinner than in a second region. The Threshold Voltage, Vth, is larger in the first region than in the second region causing an asymmetric Vth across the length of the channel. Modeling has shown that the Vth increases along the channel from about 50 milliVolts (mV) for N-FETs (about 55 mV for a P-FETs) to about 125 mV for N-FETs (about 180 mV for P-FETs) as the channel width decreases from 4 nanometers (nm) to 2 nm.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 24, 2020
    Inventors: Choonghyun Lee, Takashi Ando, Jingyun Zhang, Pouya Hashemi, Alexander Reznicek
  • STACKED RESISTIVE MEMORY WITH INDIVIDUAL SWITCH CONTROL
    Publication number: 20200403034
    Abstract: A method for fabricating stacked resistive memory with individual switch control is provided. The method includes forming a first random access memory (ReRAM) device. The method further includes forming a second ReRAM device in a stacked nanosheet configuration on the first ReRAM device. The method also includes forming separate gate contacts for the first ReRAM device and the second ReRAM device.
    Type: Application
    Filed: June 19, 2019
    Publication date: December 24, 2020
    Inventors: Takashi Ando, Jingyun Zhang, Pouya Hashemi, Alexander Reznicek, Choonghyun Lee
  • COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE HAVING FIN FIELD EFFECT TRANSISTORS WITH A COMMON METAL GATE
    Publication number: 20200388544
    Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a separate gate structure on each of a pair of vertical fins, wherein the gate structures include a gate dielectric layer and a gate metal layer, and forming a protective liner layer on the gate structures. The method further includes heat treating the pair of gate structures, and replacing the protective liner layer with an encapsulation layer. The method further includes exposing a portion of the gate dielectric layer by recessing the encapsulation layer. The method further includes forming a top source/drain on the top surface of one of the pair of vertical fins, and subjecting the exposed portion of the gate dielectric layer to a second heat treatment conducted in an oxidizing atmosphere.
    Type: Application
    Filed: June 5, 2019
    Publication date: December 10, 2020
    Inventors: Takashi Ando, Choonghyun Lee, Pouya Hashemi, Jingyun Zhang
  • ASYMMETRIC THRESHOLD VOLTAGES IN SEMICONDUCTOR DEVICES
    Publication number: 20200381520
    Abstract: Semiconductor devices and methods of forming the same include forming an inner spacer on a semiconductor fin. Two outer spacers are formed around the inner spacer, with one outer spacer being in contact with the inner spacer and with the other outer spacer being separated from the inner spacer by a gap. A dipole-forming layer is formed on the semiconductor fin in the gap. The inner spacer is etched away. A gate stack is formed on the semiconductor fin, between the outer spacers.
    Type: Application
    Filed: May 29, 2019
    Publication date: December 3, 2020
    Inventors: Takashi Ando, Alexander Reznicek, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi
  • THRESHOLD VOLTAGE ADJUSTMENT BY INNER SPACER MATERIAL SELECTION
    Publication number: 20200381305
    Abstract: Semiconductor devices and methods of forming the same include partially etching sacrificial layers in a first stack of alternating sacrificial layers and channel layers to form first recesses. A first inner spacer sub-layer is formed in the first recesses from a first dielectric material. A second inner spacer sub-layer is formed in the first recesses from a second dielectric material, different from the first dielectric material. The sacrificial layers are etched away. The first inner spacer sub-layer is etched away. A gate stack is formed on and around the channel layers and in contact with the second inner spacer sub-layer.
    Type: Application
    Filed: May 29, 2019
    Publication date: December 3, 2020
    Inventors: Takashi Ando, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi