Patents by Inventor Prabal Kanti Bhattacharya

Prabal Kanti Bhattacharya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9020797
    Abstract: A method is provided that comprises a circuit design that includes multiple design blocks; a power intent specification file that defines a power domain within the circuit design and that identifies design instances within the power domain and that defines a control function to selectively transition the defined power domain between multiple respective power supply values; using a digital simulator to simulate operation of the digital representation while using an analog simulator to simulate operation of the analog representation; wherein simulating the digital representation includes transitioning the defined power domain between supply values from among the multiple respective supply values; wherein simulating the analog representation includes periodically storing in a storage location a power supply value currently in use during digital simulation of the digital representation; and wherein simulating the analog representation includes using the stored currently in use power supply value to supply voltage
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: April 28, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Qingyu Lin, Prabal Kanti Bhattacharya, Nan Zhang, Zhong Fan
  • Patent number: 8832612
    Abstract: A method is provided to convert an analog mixed-signal schematic design to a digital netlist: digital blocks within the schematic design are converted to digital netlist modules; analog blocks within the schematic design are converted to analog netlist modules: at least one digital netlist module includes a first identifier for a component that is shared between at least one digital block and at least one analog block within the schematic design; an analog netlist module that corresponds to the at least one analog block within the design includes a second identifier for the shared component that is different from the first identifier; the analog netlist modules are converted to corresponding digital netlist modules; the first identifier is substituted for the second identifier in the course of translating the analog netlist module that corresponds to the at least one analog block.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: September 9, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Donald J. O'Riordan, Prabal Kanti Bhattacharya, Timothy Martin O'Leary
  • Publication number: 20130338991
    Abstract: A method is provided that comprises a circuit design that includes multiple design blocks; a power intent specification file that defines a power domain within the circuit design and that identifies design instances within the power domain and that defines a control function to selectively transition the defined power domain between multiple respective power supply values; using a digital simulator to simulate operation of the digital representation while using an analog simulator to simulate operation of the analog representation; wherein simulating the digital representation includes transitioning the defined power domain between supply values from among the multiple respective supply values; wherein simulating the analog representation includes periodically storing in a storage location a power supply value currently in use during digital simulation of the digital representation; and wherein simulating the analog representation includes using the stored currently in use power supply value to supply voltage
    Type: Application
    Filed: June 14, 2012
    Publication date: December 19, 2013
    Applicant: Cadence Design Systems, Inc.
    Inventors: Qingyu Lin, Prabal Kanti Bhattacharya, Nan Zhang, Zhong Fan
  • Patent number: 8601412
    Abstract: A method is provided to convert an analog mixed-signal schematic design to a digital netlist: digital blocks within the schematic design are converted to digital netlist modules; analog blocks within the schematic design are converted to analog netlist modules: at least one digital netlist module includes a first identifier for a component that is shared between at least one digital block and at least one analog block within the schematic design; an analog netlist module that corresponds to the at least one analog block within the design includes a second identifier for the shared component that is different from the first identifier; the analog netlist modules are converted to corresponding digital netlist modules; the first identifier is substituted for the second identifier in the course of translating the analog netlist module that corresponds to the at least one analog block.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: December 3, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Donald J. O'Riordan, Prabal Kanti Bhattacharya, Timothy Martin O'Leary