Patents by Inventor Prabhakar P. Tripathi

Prabhakar P. Tripathi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6893962
    Abstract: A method of forming a metallization interconnection system within a via. A first liner layer of titanium is deposited to a first thickness in the following manner. A substrate containing the via is placed within an ion metal plasma deposition chamber that contains a titanium target. The ion metal plasma deposition chamber is evacuated to a first base pressure. A first flow of argon is introduced to the ion metal plasma deposition chamber at a first deposition pressure. The substrate is biased to a first voltage. A plasma within the ion metal plasma deposition chamber is energized at a first power for a first length of time. A second liner layer of TixNy is deposited to a second thickness on top of the first liner layer of titanium in the following manner. A first flow of nitrogen and a second flow of argon are introduced to the ion metal plasma deposition chamber at a second deposition pressure. The substrate is biased to a second voltage.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: May 17, 2005
    Assignee: LSI Logic Corporation
    Inventors: Prabhakar P. Tripathi, Zhihai Wang, Weidan Li
  • Publication number: 20030203622
    Abstract: A method of forming a metallization interconnection system within a via. A first liner layer of titanium is deposited to a first thickness in the following manner. A substrate containing the via is placed within an ion metal plasma deposition chamber that contains a titanium target. The ion metal plasma deposition chamber is evacuated to a first base pressure. A first flow of argon is introduced to the ion metal plasma deposition chamber at a first deposition pressure. The substrate is biased to a first voltage. A plasma within the ion metal plasma deposition chamber is energized at a first power for a first length of time. A second liner layer of TixNy is deposited to a second thickness on top of the first liner layer of titanium in the following manner. A first flow of nitrogen and a second flow of argon are introduced to the ion metal plasma deposition chamber at a second deposition pressure. The substrate is biased to a second voltage.
    Type: Application
    Filed: March 27, 2003
    Publication date: October 30, 2003
    Applicant: LSI Logic Corporation
    Inventors: Prabhakar P. Tripathi, Zhihai Wang, Weidan Li
  • Patent number: 6569751
    Abstract: A method of forming a metallization interconnection system within a via. A first liner layer of titanium is deposited to a first thickness in the following manner. A substrate containing the via is placed within an ion metal plasma deposition chamber that contains a titanium target. The ion metal plasma deposition chamber is evacuated to a first base pressure. A first flow of argon is introduced to the ion metal plasma deposition chamber at a first deposition pressure. The substrate is biased to a first voltage. A plasma within the ion metal plasma deposition chamber is energized at a first power for a first length of time. A second liner layer of TixNy is deposited to a second thickness on top of the first liner layer of titanium in the following manner. A first flow of nitrogen and a second flow of argon are introduced to the ion metal plasma deposition chamber at a second deposition pressure. The substrate is biased to a second voltage.
    Type: Grant
    Filed: July 17, 2000
    Date of Patent: May 27, 2003
    Assignee: LSI Logic Corporation
    Inventors: Prabhakar P. Tripathi, Zhihai Wang, Weidan Li
  • Patent number: 6109775
    Abstract: Disclosed is the formation of additional lines, either dummy lines or active lines, in an electrically conductive pattern of lines to provide more uniform loading for either etching or chemical/mechanical polishing of a layer of electrically conductive material from which the pattern of lines is formed. Also disclosed is the use of additional or dummy vias to balance the loading during etching of the vias, as well as to provide stress relief for underlying metal in regions or areas having a low density of vias. Further disclosed is the use of a working grid on the integrated circuit structure to analyze the spacing of lines or vias for the above effects.
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: August 29, 2000
    Assignee: LSI Logic Corporation
    Inventors: Prabhakar P. Tripathi, Keith Chao, Ratan K. Choudhury, Gauri C. Das, Nicholas K. Eib, Ashok K. Kapoor, Thomas G. Mallon
  • Patent number: 5776831
    Abstract: A method of forming a metallization system in which ohmic contact is made to a silicon surface is described. A first layer of titanium is formed over the silicon surface. This first titanium layer is subsequently annealed in a nitrogen atmosphere to convert a first portion of the layer to a layer of titanium silicide, and a second portion to a first layer of titanium nitride. The titanium silicide layer provides for the formation of an ohmic contact between the metallization system and the silicon surface. The first titanium nitride layer provides for a degree of spike resistance between the silicon surface and the metallization system. A second layer of titanium nitride is formed over the first titanium nitride layer. This second titanium nitride layer provides further spike resistance between the silicon surface and the metallization system.
    Type: Grant
    Filed: December 27, 1995
    Date of Patent: July 7, 1998
    Assignee: LSI Logic Corporation
    Inventors: Gobi R. Padmanabhan, Prabhakar P. Tripathi
  • Patent number: 5654897
    Abstract: A method of interactive feedback in semiconductor processing is provided which compensates for lithographic proximity effects, reactive ion etch loading effects, electromigration and stress due to layering.
    Type: Grant
    Filed: December 5, 1995
    Date of Patent: August 5, 1997
    Assignee: LSI Logic Corporation
    Inventors: Prabhakar P. Tripathi, Bruce Whitefield, Chi-Hung Wang
  • Patent number: 5477466
    Abstract: A method of interactive feedback in semiconductor processing is provided which compensates for lithographic proximity effects, reactive ion etch loading effects, electromigration and stress due to layering.
    Type: Grant
    Filed: December 22, 1994
    Date of Patent: December 19, 1995
    Assignee: LSI Logic Corporation
    Inventors: Prabhakar P. Tripathi, Bruce Whitefield, Chi-Hung Wang
  • Patent number: 5379233
    Abstract: A method of interactive feedback in semiconductor processing is provided which compensates for lithographic proximity effects, reactive ion etch loading effects, electromigration and stress due to layering.
    Type: Grant
    Filed: July 19, 1991
    Date of Patent: January 3, 1995
    Assignee: LSI Logic Corporation
    Inventors: Prabhakar P. Tripathi, Bruce Whitefield, Chi-Hung Wang