Abstract: Device features, such as gate lengths and channel widths, are selectively altered by first identifying those devices within a semiconductor die that exhibit physical attributes, e.g., leakage current and threshold voltage magnitude, that are different than previously verified by a design/simulation tool used to design the devices. The identified, non-conforming devices are then further identified by the amount of deviation from the original design goal that is exhibited by each non-conforming device. The non-conforming devices are then mathematically categorized into bins, where each bin is tagged with a magnitude of deviation from a design goal. The mask layers defining the features of the non-conforming devices are then selectively modified by an amount that is commensurate with the tagged deviation. The selectively modified mask layers are then used to generate a new semiconductor die that exhibits improved performance.

Abstract: A method of removing a defect from a gate stack on a substrate, comprises treating the gate stack with a plasma. The plasma comprises fluorine, the gate stack comprises a gate layer and a metallic layer, and substantially no photoresist is present on the substrate.

Abstract: According to one embodiment (100), a method of forming borderless contacts may include forming a composite layer over a first insulating layer (102). A contact hole may be formed through a composite layer and a first insulating layer (104). A conducting layer may then be formed (106), including within a contact hole. Portions of a conducting layer may then be removed with a composite layer as a polish stop (108), and a contact structure may be formed. A first interconnect structure and a second insulating layer may then be formed over a first insulating layer (110 and 112). A borderless contact pattern may then be etched with a composite layer as an etch stop (114).

Abstract: In one embodiment, a gate of a transistor is formed by performing a first thermal treatment on a silicon layer, forming a metal stack over the silicon layer, and performing a second thermal treatment on the metal stack. The first thermal treatment may be a rapid thermal annealing step, while the second thermal treatment may be a rapid thermal nitridation step. The resulting gate exhibits relatively low interface contact resistance between the silicon layer and the metal stack, and may thus be advantageously employed in high-speed devices.

Abstract: In one embodiment, a transistor is fabricated by forming a sacrificial emitter over a base, forming an oxide layer over the sacrificial emitter, removing a portion of the oxide layer, and then removing the sacrificial emitter. An emitter is later formed in the space formerly occupied by the sacrificial emitter. The sacrificial emitter allows a base implant step to be performed early in the process using a single masking step. The base may comprise epitaxial silicon-germanium or silicon.

Abstract: A method for fabricating a bipolar transistor is provided. In some cases, the method may include patterning an epitaxial layer to expose one or more regions of a semiconductor topography. The method may further include depositing an intermediate layer above the exposed regions and remaining portions of the epitaxial layer. A conductive emitter structure may then be formed above and within the intermediate layer. In another embodiment, the method may include etching a first dielectric layer in alignment with a patterned base of a bipolar transistor while simultaneously etching a second dielectric layer in alignment with a patterned emitter structure of the bipolar transistor. In yet other embodiments, the method may include depositing an intermediate layer which is substantially etch resistant to a resist stripping process. In addition or alternatively, the intermediate layer may include etch characteristics that are substantially similar to a conductive layer formed above the intermediate layer.

Abstract: In one embodiment, a gate of a transistor is formed by performing a first thermal treatment on a silicon layer, forming a metal stack over the silicon layer, and performing a second thermal treatment on the metal stack. The first thermal treatment may be a rapid thermal annealing step, while the second thermal treatment may be a rapid thermal nitridation step. The resulting gate exhibits relatively low interface contact resistance between the silicon layer and the metal stack, and may thus be advantageously employed in high-speed devices.

Abstract: A method is provided which includes forming a deep isolation structure within a semiconductor topography. In some cases, the method may include forming a first isolation structure within a semiconductor layer and etching an opening within the isolation structure to expose the semiconductor layer. In addition, the method may include etching the semiconductor layer to form a trench extending through the isolation structure and at least part of the semiconductor layer. In some cases, the method may include removing part of a first fill layer deposited within the trench such that an upper surface of the fill layer is below an upper portion of the trench. In such an embodiment, the vacant portion of the trench may be filled with a second fill layer. In yet other embodiments, the method may include planarizing the first fill layer within the trench and subsequently oxidizing an upper portion of the fill layer.