Abstract: Current inspection processes employed for pipeline networks data acquisition aided with manually locating and recording defects/observations, thus leading labor intensive, prone to error and a time-consuming task thereby resulting in process inefficiencies. Embodiments of the present disclosure provide systems and methods for that leverage artificial intelligence/machine learning models and image processing techniques to automate log and data processing, reports and insights generation thereby reduce dependency on manual analysis, improve annual productivity of survey meterage and bring in process and cost efficiencies into overall asset health management for utilities, thereby enhancing accuracy in defect identification, analysis, classification thereof.

Abstract: Current inspection processes employed for pipeline networks data acquisition aided with manually locating and recording defects/observations, thus leading labor intensive, prone to error and a time-consuming task thereby resulting in process inefficiencies. Embodiments of the present disclosure provide systems and methods for that leverage artificial intelligence/machine learning models and image processing techniques to automate log and data processing, reports and insights generation thereby reduce dependency on manual analysis, improve annual productivity of survey meterage and bring in process and cost efficiencies into overall asset health management for utilities, thereby enhancing accuracy in defect identification, analysis, classification thereof.

Abstract: Methods and systems are disclosed for determining mask-value pairs for controlling access to a memory segment for a plurality of IDs. A first set of mask-value pairs is determined for a set of allowed identifiers (IDs) and a set of non-allowed IDs. Each mask-value pair of the first set matches at least one ID of the set of allowed IDs and does not match any of the IDs of the set of non-allowed IDs. Redundant mask-value pairs are removed from the first set to produce a second set. Subsets of mask-value pairs in the second set that match the entire set of allowed IDs are determined. The subset having the highest processing efficiency is determined and selected. A set of configuration data is generated that is configured to cause a memory management circuit to enforce access to the memory segment based on the selected subset of mask-value pairs.

Abstract: Various example implementations are directed to circuits and methods for partitioning a memory for a circuit design in a programmable IC. A user interface is provided for a user to define subsystems, master circuits, memory segments, and permissions for accessing the memory segments by the master circuits. For each defined memory segment, a respective access control entry is generated that includes data for determining master circuits that are permitted access to the memory segment by the user-defined permissions. A first portion of configuration data is generated that is configured to cause a memory management circuit in the programmable IC to enforce access to address ranges, corresponding to the respective memory segments, in a memory of the programmable IC according to the respective access control entries. A second portion of configuration data is generated that is configured to cause programmable resources of the programmable IC to implement the circuit design.

Abstract: A client receives map objects that define respective physical objects of a floor plan of a building, including a floor plan outer boundary, one or more rooms, and connected pathways traversable by a person. The client renders, in scalable vector graphic form, the map objects into a map of the floor plan that depicts the respective physical objects, including the one or more rooms, the connected pathways, and the outer boundary. The client displays the map. The client receives an update message that defines a change to the floor plan with respect to a map object identified in the update message, and renders the change with respect to the identified map object into the map to depict the change on the map without rendering any other ones of the map objects that were previously rendered into the map. The client displays the map with the change depicted on the map.

Abstract: In an approach for determining multiplier values and divisor values for programming frequency multiplier and divider circuits in a clock network, respective requested frequency values and respective tolerance levels relative to the requested frequency values for a plurality of clocked circuit blocks are used. Multiple solution sets are generated, with each solution set including a multiplier value and an associated set of values of divisors, such that resulting actual frequencies satisfy the respective tolerance levels. Respective sets of clocked error values are determined for the plurality of solution sets, with each clocked error value corresponding to a clocked circuit block. Solution-set-error values are determined as a function of the respective sets of clocked error values, and the solution set having the least solution-set-error value is selected and stored.

Abstract: Hierarchical preset and rule base configuration of a system-on-chip (SOC) includes receiving a user input selecting a first circuit block of the SOC for enablement and determining, using a processor, a first top level preset according to the user input for the first circuit block. Selected intermediate presets are determined from a plurality of hierarchically ordered presets for the first circuit block. Low level presets are automatically determined for the first circuit block according to the selected intermediate presets for the first circuit block. The low level presets are output, e.g., by loading them into the SOC.

Abstract: Techniques for efficient KASUMI ciphering are disclosed. In one aspect, one KASUMI round for generating a fractional portion of the KASUMI cipher is deployed with appropriate feedback such that eight sequential rounds produce the KASUMI output. In another aspect, one third of the FO function is deployed with appropriate feedback such that three successive cycles produce the FO output. In yet another aspect, the FI function is deployed with appropriate feedback such that two subsequent cycles produce the FI output. In yet another aspect, a sub-key generator comprising two shift registers produces sub-keys for each round and sub-stage thereof in an efficient manner. These aspects, collectively, yield the advanced benefits of low area and low cost implementations of KASUMI with a simple user interface. Various other aspects of the invention are also presented.

Abstract: Techniques for efficient KASUMI ciphering are disclosed. In one aspect, one KASUMI round for generating a fractional portion of the KASUMI cipher is deployed with appropriate feedback such that eight sequential rounds produce the KASUMI output. In another aspect, one third of the FO function is deployed with appropriate feedback such that three successive cycles produce the FO output. In yet another aspect, the FI function is deployed with appropriate feedback such that two subsequent cycles produce the FI output. In yet another aspect, a sub-key generator comprising two shift registers produces sub-keys for each round and sub-stage thereof in an efficient manner. These aspects, collectively, yield the advanced benefits of low area and low cost implementations of KASUMI with a simple user interface. Various other aspects of the invention are also presented.