Abstract: An aerated confection containing particulate material and method for making the same is disclosed. The method allows the incorporation of particulate material at a level of from 1 to 50.0% by weight based on the total weight of the aerated confection. The aerated confection preferably includes hexametaphosphate as a gel-stiffening agent.

Abstract: A polishing pad for chemical mechanical planarization of a film on a substrate is customized by obtaining one or more characteristics of a structure on a substrate. For example, when the structure is a chip formed on a semiconductor wafer, the one or more characteristics of the structure can include chip size, pattern density, chip architecture, film material, film topography, and the like. Based on the one or more characteristics of the structure, a value for the one or more chemical or physical properties of the pad is selected. For example, the one or more chemical or physical properties of the pad can include pad material hardness, thickness, surface grooving, pore size, porosity, Youngs modulus, compressibility, asperity, and the like.

Abstract: Disclosed are processes for stabilizing omega-3 fatty acids for use in food products. The processes permit creation of a variety of food forms and food ingredients that contain omega-3 fatty acids like docosahexaenoic acid and eicosapentaenoic acid wherein these foods and food forms are stable for months without developing fishy aromas or tastes. This stability enables the incorporation of omega-3 fatty acids into food forms such as ready to eat cereals, trail mixes, chips, granola bars, toaster pastries, baked goods, cookies, crackers, fruit pieces and fruit leathers. The processes utilize a zein coating to protect and stabilize the omega-3 fatty acids.

Abstract: A method of manufacture for semiconductor electronic products and a circuit structure. A semiconductor material has a surface region and dopant is provided to a portion of the surface region. The portion of the surface region provided with the dopant is irradiated with sufficient energy to induce diffusion of the dopant from the portion of the surface region to another region of the semiconductor material. A method for manufacturing an electronic product with a semiconductor material having a surface and two spaced-apart regions along the surface for receiving dopant includes forming a field effect transistor gate structure is along the surface and over a third region of the surface between the two spaced-apart regions. Dopant is provided to the spaced-apart regions which are heated to a temperature at least 50 degrees C. higher than the peak temperature which results in the third region when the spaced-apart regions are heated.

Abstract: The present application relates to polishing pads for chemical mechanical planarization (CMP) of substrates, and methods of fabrication and use thereof. The pads described in this invention are customized to polishing specifications where specifications include (but not limited to) to the material being polished, chip design and architecture, chip density and pattern density, equipment platform and type of slurry used. These pads can be designed with a specialized polymeric nano-structure with a long or short range order which allows for molecular level tuning achieving superior themo-mechanical characteristics. More particularly, the pads can be designed and fabricated so that there is both uniform and nonuniform spatial distribution of chemical and physical properties within the pads.

Abstract: Various examples of customized polishing pads are given, along with methods of making and using such customized polishing pads. The subject customized pads are designed and fabricated so that there is spatial distribution of chemical and physical properties of the pads that are customized for performance suited to a specific type of substrate, as well as fabrication control in implementing such customized design. Such customized design and fabrication control produce a monolithic pad thereby specifically suited to provide uniform performance of CMP of the targeted substrate.

Abstract: Methods for producing in-situ grooves in CMP pads are provided. In general, the methods for producing in-situ grooves comprise the steps of patterning a silicone lining, placing the silicone lining in, or on, a mold, adding CMP pad material to the silicone lining, and allowing the CMP pad to solidify. CMP pads comprising novel groove designs are also described. For example, described here are CMP pads comprising concentric circular grooves and axially curved grooves, reverse logarithmic grooves, overlapping circular grooves, lassajous groves, double spiral grooves, and multiply overlapping axially curved grooves. The CMP pads may be made from polyurethane, and the grooves produced therein may be made by a method from the group consisting of silicone lining, laser writing, water jet cutting, 3-D printing, thermoforming, vacuum forming, micro-contact printing, hot stamping, and mixtures thereof.

Abstract: A method is disclosed for preparing an expanded, vacuum puffed, dried fruit product. The method includes infusing the fruit with a low Brix infusion solution and then expanding the fruit by subjecting it to a vacuum at elevated temperature followed by drying of the fruit under a vacuum at elevated temperature and finally cooling of the fruit under lowered temperature while maintaining the vacuum. The product produced by the method is light, crisp, and has a low water activity and a low buoyant density.

Abstract: A method for using a silicon germanium (SiGe) surface layer to integrate a high-k dielectric layer into a semiconductor device. The method forms a SiGe surface layer on a substrate and deposits a high-k dielectric layer on the SiGe surface layer. An oxide layer, located between the high-k dielectric layer and an unreacted portion of the SiGe surface layer, is formed during one or both of deposition of the high-k dielectric layer and an annealing process after deposition of the high-k dielectric layer. The method further includes forming an electrode layer on the high-k dielectric layer.

Abstract: A SiGe thin layer semiconductor structure containing a substrate having a dielectric layer, a variable composition SixGe1-x layer on dielectric layer, and a Si cap layer on the variable composition SixGe1-x layer. The variable composition SixGe1-x layer can contain a SixGe1-x layer with a graded Ge content or a plurality of SixGe1-x sub-layers each with different Ge content. In one embodiment of the invention, the SiGe thin layer semiconductor structure contains a semiconductor substrate having a dielectric layer, a Si-containing seed layer on the dielectric layer, a variable composition SixGe1-x layer on the seed layer, and a Si cap layer on the variable composition SixGe1-x layer. A method and processing tool for fabricating the SiGe thin layer semiconductor structure are also provided.

Abstract: A method for forming an oxide layer on a vertical, non-planar semiconductor surface provides a low stress oxide layer having a pristine interface characterized by a roughness of less than 3 angstroms. The oxide layer includes a portion that is substantially amorphous and notably dense. The oxide layer is a graded growth oxide layer including a composite of a first oxide portion formed at a relatively low temperature below the viscoelastic temperature of the oxide film and a second oxide portion formed at a relatively high temperature above the viscoelastic temperature of the oxide film. The process for forming the oxide layer includes thermally oxidizing at a first temperature below the viscoelastic temperature of the film, and slowly ramping up the temperature to a second temperature above the viscoelastic temperature of the film and heating at the second temperature.

Abstract: A multi-piece food product (10) comprising a plurality of strands (12A-12K) that are extruded and aggregated to form an aesthetically pleasing food product is provided. A formulation used to make each of the strands (12A-12K) includes a mixture comprising at least 20% sweetener, at least 15% starchy material, and at least 1% fruit by weight based a total dry weight of the mixture to yield a starch-based confectionary food product. One process for forming the multi-piece food product (10) includes extruding a food stream from a slurry, dividing the food stream into three separate food streams (24A, 24B), injecting color, flavor, and ascorbic acid into the food streams (24A, 24B), conveying the food streams (24A, 24B) into a former (26) and extruding the strands (12A-12K) therefrom, forming the strands (12A, 12B) into an aggregate food mass (31), cooling the food mass (31), and cutting the food mass (31) into individual portions.

Abstract: This invention provides a method for modifying the surface properties of a Si or Si alloy substrate by performing repeated etch-grow cycles of thermal oxide to yield a more defect free substrate with a more uniform nucleating surface which provides an improved interface for dielectric formation. Additionally, this method of processing does not expose the substrate to ambient atmosphere and preserves the improved surface until subsequent processing steps are performed.

Abstract: A polishing pad for chemical mechanical planarization of a film on a substrate is customized by obtaining one or more characteristics of a structure on a substrate. For example, when the structure is a chip formed on a semiconductor wafer, the one or more characteristics of the structure can include chip size, pattern density, chip architecture, film material, film topography, and the like. Based on the one or more characteristics of the structure, a value for the one or more chemical or physical properties of the pad is selected. For example, the one or more chemical or physical properties of the pad can include pad material hardness, thickness, surface grooving, pore size, porosity, Youngs modulus, compressibility, asperity, and the like.

Abstract: An aerated confection containing particulate material and method for making the same is disclosed. The method allows the incorporation of particulate material at a level of from 1 to 50.0% by weight based on the total weight of the aerated confection. The aerated confection preferably includes hexametaphosphate as a gel-stiffening agent.

Abstract: An aerated confection containing high levels of fruit solids and method for making the same is disclosed. The method allows the incorporation of fruit solids at a level of from 0.5 to 20.0% by weight on a dry weight basis making the aerated confection similar to that of most real fruits. The aerated confection preferably includes hexametaphosphate as a gel-stiffening agent.

Abstract: A memory cell of a non-volatile memory includes a control gate oxide layer having graded portions with greatly reduced stress on a polysilicon floating gate layer. The method of making the control gate oxide layer preferably includes growing a first oxide portion by upwardly ramping the polysilicon floating gate layer to a first temperature lower than a glass transition temperature, and exposing the polysilicon floating gate layer to an oxidizing ambient at the first temperature and for a first time period. Also, the method includes growing a second oxide portion between the first oxide portion and the polysilicon floating gate layer by exposing the polysilicon floating gate layer to an oxidizing ambient at a second temperature higher than the glass transition temperature for a second time period. The second oxide portion may have a thickness in a range of about 25 to 75% of a total thickness of the graded, grown, control gate oxide layer.

Abstract: A memory cell of a non-volatile memory includes a tunnel oxide layer having graded portions with greatly reduced stress on a silicon substrate. The method of making the tunnel oxide preferably includes growing a first oxide portion by upwardly ramping the silicon substrate to a first temperature lower than a glass transition temperature, and exposing the silicon substrate to an oxidizing ambient at the first temperature and for a first time period. Also, the method includes growing a second oxide portion between the first oxide portion and the silicon substrate by exposing the silicon substrate to an oxidizing ambient at a second temperature higher than the glass transition temperature for a second time period. The second oxide portion may have a thickness in a range of about 2 to 50% of a total thickness of the graded, grown, tunnel oxide layer.

Abstract: A bipolar transistor includes an oxide layer having graded portions with greatly reduced stress on a silicon substrate. The method of making the oxide preferably includes growing a first oxide portion by upwardly ramping the silicon substrate to a first temperature lower than a glass transition temperature, and exposing the silicon substrate to an oxidizing ambient at the first temperature and for a first time period. Also, the method includes growing a second oxide portion between the first oxide portion and the silicon substrate by exposing the silicon substrate to an oxidizing ambient at a second temperature higher than the glass transition temperature for a second time period. The second oxide portion may have a thickness in a range of about 2 to 75% of a total thickness of the graded, grown, oxide layer. The step of upwardly ramping preferably includes upwardly ramping the temperature at a relatively high ramping rate to reduce any oxide formed during the upward ramping.

Abstract: A vector and in particular a virus, plasmid or oligonucleotide vector including unique enhancer and promoter domains. The vectors of the invention are derived from a retrovirus or feline endogenous proviral elements. The unique enhancer domains exhibit unique tissue specificity. These vectors are useful in gene therapy or gene transfer techniques.