Abstract: Convolutional neural network (CNN) components can operate to provide various speed-ups to improve upon or operate as part of an artificial neural network (ANN). A convolution component performs convolution operations that extract data from one or more images, and provides the data to one or more rectified linear units (RELUs). The RELUs are configured to generate non-linear convolution output data. A pooling component generates pooling outputs in parallel with the convolution operations via a pipelining process based on a pooling window for a subset of the non-linear convolution output data. A fully connected (FC) component configured to form an artificial neural network (ANN) that provides ANN outputs based on the pooling outputs and enables a recognition of a pattern in the one or more images based on the ANN outputs. Layers of the FC component are also able to operate in parallel in another pipelining process.

Abstract: A microcontroller that can be configured to selectively operate in a synchronous mode or an asynchronous mode, and a method of selectively switching the operating mode is described. The microcontroller can include a processor and a system controller. The processor can be configured to operate synchronously in a synchronous operating mode and asynchronously in an asynchronous operating mode. The processor can also be configured to generate a processor idle status signal indicative of the processor operating in a reduced power mode, and generate a programming signal. The system controller can be configured to generate an asynchronous mode signal based on the programming signal and the processor idle status signal, and provide the asynchronous mode signal to the processor to control the processor to selectively operate in the synchronous operating mode and in the asynchronous operating mode.

Abstract: A method and system to reduce power consumption are described. The system can include a first device and a second device of a plurality of devices. The second device can be coupled to the first device via an interconnect. A serialization capability of the first device can be determined. Further, access to the second device one or more of the plurality of devices can be determined. The interconnect can be serialized based on the determined serialization capability and/or the determined access to the second device.

Abstract: Convolutional neural network (CNN) components can operate to provide various speed-ups to improve upon or operate as part of an artificial neural network (ANN). A convolution component performs convolution operations that extract data from one or more images, and provides the data to one or more rectified linear units (RELUs). The RELUs are configured to generate non-linear convolution output data. A pooling component generates pooling outputs in parallel with the convolution operations via a pipelining process based on a pooling window for a subset of the non-linear convolution output data. A fully connected (FC) component configured to form an artificial neural network (ANN) that provides ANN outputs based on the pooling outputs and enables a recognition of a pattern in the one or more images based on the ANN outputs. Layers of the FC component are also able to operate in parallel in another pipelining process.

Abstract: A method and system to reduce power consumption are described. The system can include a first device and a second device of a plurality of devices. The second device can be coupled to the first device via an interconnect. A serialization capability of the first device can be determined. Further, access to the second device one or more of the plurality of devices can be determined. The interconnect can be serialized based on the determined serialization capability and/or the determined access to the second device.

Abstract: A method and system to reduce power consumption are described. The system can include a first device and a second device of a plurality of devices. The second device can be coupled to the first device via an interconnect. A serialization capability of the first device can be determined. Further, access to the second device one or more of the plurality of devices can be determined. The interconnect can be serialized based on the determined serialization capability and the determined access to the second device.

Abstract: A microcontroller that can be configured to selectively operate in a synchronous mode or an asynchronous mode, and a method of selectively switching the operating mode is described. The microcontroller can include a processor and a system controller. The processor can be configured to operate synchronously in a synchronous operating mode and asynchronously in an asynchronous operating mode. The processor can also be configured to generate a processor idle status signal indicative of the processor operating in a reduced power mode, and generate a programming signal. The system controller can be configured to generate an asynchronous mode signal based on the programming signal and the processor idle status signal, and provide the asynchronous mode signal to the processor to control the processor to selectively operate in the synchronous operating mode and in the asynchronous operating mode.

Abstract: A method and system to reduce power consumption are described. The system can include a first device and a second device of a plurality of devices. The second device can be coupled to the first device via an interconnect. A serialization capability of the first device can be determined. Further, access to the second device one or more of the plurality of devices can be determined. The interconnect can be serialized based on the determined serialization capability and the determined access to the second device.

Abstract: Representative implementations of devices and techniques provide dynamic secure sharing of resources. A resource module can be partitioned into a plurality of functional blocks, which may be allocated to non-secure and secure applications. A security monitor can monitor processor activity and determine when secure resources may be accessed.

Abstract: Disclosed herein are techniques related to control of a system. According to some embodiments the system includes a plurality of elements and a power supply to supply power to the elements. According to some embodiments the method comprises: delivering a clock signal to a subset of elements, the clock signal defining a sequence of clock pulses; determining, for a first clock pulse, elements in the subset to consume power; and controlling the power supply. A system is disclosed having a plurality of elements including a subset of elements, a power supply to supply power to the elements, a clock signal delivery configured to deliver a clock signal to the subset of elements in the plurality of elements, and a control module configured to control the power supply based on the determining elements to consume power. An apparatus and a device for use in a system are also disclosed.

Abstract: The present disclosure relates to some aspects relate to a method for detecting stack memory corruption. In some embodiments, the method comprises determining an expected memory range of a data element that is to be written to a stack memory by tracking changes to a stack pointer. The determined memory range is stored in a stack object database. Upon receiving a stack memory access related instruction (e.g., LOAD/STORE instruction or arithmetic instruction operating on memory addresses) to write data to the stack memory, an address of the memory location to be accessed is determined. If the address falls within the expected memory range, no stack corruption is present. However, if the address falls outside of the expected memory range, stack corruption is present. Therefore, the present method provides for real time detection of corruption (e.g., overrun and underrun errors) in stack memory.

Abstract: One embodiment of the present invention relates to a heap overflow detection system that includes an arithmetic logic unit, a datapath, and address violation detection logic. The arithmetic logic unit is configured to receive an instruction having an opcode and an operand and to generate a final address and to generate a compare signal on the opcode indicating a heap memory access related instruction. The datapath is configured to provide the opcode and the operand to the arithmetic logic unit. The address violation detection logic determines whether a heap memory access is a violation according to the operand and the final address on receiving the compare signal from the arithmetic logic unit.

Abstract: Representative implementations of devices and techniques provide dynamic secure sharing of resources. A resource module can be partitioned into a plurality of functional blocks, which may be allocated to non-secure and secure applications. A security monitor can monitor processor activity and determine when secure resources may be accessed.

Abstract: The present disclosure relates to some aspects relate to a method for detecting stack memory corruption. In some embodiments, the method comprises determining an expected memory range of a data element that is to be written to a stack memory by tracking changes to a stack pointer. The determined memory range is stored in a stack object database. Upon receiving a stack memory access related instruction (e.g., LOAD/STORE instruction or arithmetic instruction operating on memory addresses) to write data to the stack memory, an address of the memory location to be accessed is determined. If the address falls within the expected memory range, no stack corruption is present. However, if the address falls outside of the expected memory range, stack corruption is present. Therefore, the present method provides for real time detection of corruption (e.g., overrun and underrun errors) in stack memory.

Abstract: One embodiment of the present invention relates to a heap overflow detection system that includes an arithmetic logic unit, a datapath, and address violation detection logic. The arithmetic logic unit is configured to receive an instruction having an opcode and an operand and to generate a final address and to generate a compare signal on the opcode indicating a heap memory access related instruction. The datapath is configured to provide the opcode and the operand to the arithmetic logic unit. The address violation detection logic determines whether a heap memory access is a violation according to the operand and the final address on receiving the compare signal from the arithmetic logic unit.