Abstract: A ring network with an automatic protection switching domain includes a control VLAN and at least one data VLAN. A master node in the ring is connected to at least one transit node. Each node in the ring network is linked to an adjacent node by a primary port or a secondary port. The master node receives notification of a fault via the control VLAN, the fault indicating a failed link between adjacent nodes. In response, the master node unblocks its secondary port to traffic on the data VLAN(s). The forwarding database entries on the master node and on the transit node(s) are flushed. Data traffic is flooded to the ring network until forwarding database entries on the master node and on the transit node(s) have been reestablished.

Abstract: A network switch automatically detects undesired network traffic and mirrors the undesired traffic to a security management device. The security management device determines the source of the undesired traffic and redirects traffic from the source to itself. The security management device also automatically sends a policy to a switch to block traffic from the source.

Abstract: A method and system is provided for inter-domain loop protection using a hierarchy of loop resolving protocols. The method includes receiving messages from inter-domain switches. The inter-domain switches belong to a plurality of loop-free network topology domains. A logical domain is abstracted that includes the inter-domain switches and logical links that connect the switches. Each logical link represents one of the physical loop free network topology domains that the inter-domain switches belong to. Then, the loops in the logical domain are eliminated. One or more logical links and ports associated with those logical links may be blocked to break the loops. This provides for a network free of inter-domain loops.

Abstract: A method and system is provided for inter-domain loop protection using a hierarchy of loop resolving protocols. The method includes receiving messages from inter-domain switches. The inter-domain switches belong to a plurality of loop-free network topology domains. A logical domain is abstracted that includes the inter-domain switches and logical links that connect the switches. Each logical link represents one of the physical loop free network topology domains that the inter-domain switches belong to. Then, the loops in the logical domain are eliminated. One or more logical links and ports associated with those logical links may be blocked to break the loops. This provides for a network free of inter-domain loops.

Abstract: A control memory is provided for storing the control and state information of a number of virtual direct memory access (DMA) channels. A control memory arbiter and a control memory data bus are also provided to arbitrate accesses to the control memory to facilitate asynchronous transmit and receive. Separate areas in the control memory are provided for storing the control and state information of the transmit DMAs, and the receive DMAs. Additionally, descriptive information about the transmit/receive data ring and its descriptor, the data packet being transferred and its cells are also stored for the transmit and receive DMAs. The control memory is also used to stored a programmable bandwidth group (BWG) table comprising a plurality of BWG index entries for bandwidth selection.

Abstract: A method and an apparatus for hardware and software interaction in data transfers of shared data structures in memory. The method and apparatus decreases the number of mutex lockings required to prevent conflict between different software attempting to access the same data and keeps the index value for each buffer in use in order to prevent conflicts between buffer replacement and packet arrival. In an exemplary implementation of the method and apparatus of the present invention, a receive hardware of a computer system keeps an index value for each buffer in use. This index value is placed in a completion ring protected by a mutex, and placed in a software queue protected by mutex. The mutexes assure that only one thread will possess a given index at a given time. No mutex locking is required for a buffer table containing software address and related information.