Patents by Inventor Prakash Ravikumar Bhatia

Prakash Ravikumar Bhatia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Write assist circuit integrated with leakage reduction circuit of a static random access memory for increasing the low voltage supply during write operations
    Patent number: 9542998
    Abstract: A transient voltage collapse circuit provides a reference voltage for an SRAM (static random access memory). The SRAM receives a first reference voltage and a second reference voltage higher than the first reference voltage. The transient voltage collapse circuit provides the first reference voltage to the SRAM via a voltage supply line. The transient voltage collapse circuit maintains the voltage supply line at a first voltage level during a power save mode of the SRAM. The transient voltage collapse circuit increases the voltage of the voltage supply line during a write operation of the SRAM. The increase in the voltage of the supply line reduces the gap between first reference voltage and the second reference voltage, thereby assisting with the write operation of the SRAM.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: January 10, 2017
    Assignee: Synopsys, Inc
    Inventors: Ashish Akhilesh, Yogesh Malviya, Prakash Ravikumar Bhatia
  • Memory leakage control circuit and method
    Patent number: 7760575
    Abstract: In one embodiment, a static random access memory (SRAM) is operable with first voltage and second voltages and includes a plurality of SRAM cells arranged in rows and columns, each SRAM cell being coupled to a respective wordline, respective complementary bitlines, and a source line and a control circuit connected between the source line and the second voltage. The control circuit is selectively operable in a working mode in which data in the plurality of SRAM cells can be accessed, a sleep mode is which data is retained but leakage is reduced and a shutdown mode in which the source line is allowed to float to a level that is substantially equal to the first voltage.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: July 20, 2010
    Assignee: Virage Logic Corp.
    Inventors: Michael James Tooher, Prakash Ravikumar Bhatia
  • Memory Leakage Control Circuit and Method
    Publication number: 20090168497
    Abstract: In one embodiment, a static random access memory (SRAM) is operable with first voltage and second voltages and comprises a plurality of SRAM cells arranged in rows and columns, each SRAM cell being coupled to a respective wordline, respective complementary bitlines, and a source line and a control circuit connected between the source line and the second voltage. The control circuit is selectively operable in a working mode in which data in the plurality of SRAM cells can be accessed and a shutdown mode in which the source line is allowed to float to a level that is substantially equal to the first voltage.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Inventors: Michael James Tooher, Prakash Ravikumar Bhatia