Patents by Inventor PRAKASHKUMAR GOVINDBHAI MAKWANA

PRAKASHKUMAR GOVINDBHAI MAKWANA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Verification of a bridge having a late write buffer
    Patent number: 10629285
    Abstract: Verifying a device under test (DUT) in which the DUT includes a bridge with a late write buffer includes storing write requests provided to the bridge in an initiator queue, and storing write requests provided to the target memory in a target queue. Upon both the initiator and target queues being non-empty, when entry addresses of top entries of the initiator and target queue match, data entries of the top entries of the initiator and target queue do not match, and the initiator queue has more than one entry, determining whether an entry address of a next entry in the initiator queue matches the entry address of the top entry in the initiator queue, and when the entry addresses of the next entry and the top entry in the initiator queue match, merging the top and next entry of the initiator queue and deleting the top entry of initiator queue.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: April 21, 2020
    Assignee: NXP USA, Inc.
    Inventor: Prakashkumar Govindbhai Makwana
  • VERIFICATION OF A BRIDGE HAVING A LATE WRITE BUFFER
    Publication number: 20190362802
    Abstract: Verifying a device under test (DUT) in which the DUT includes a bridge with a late write buffer includes storing write requests provided to the bridge in an initiator queue, and storing write requests provided to the target memory in a target queue. Upon both the initiator and target queues being non-empty, when entry addresses of top entries of the initiator and target queue match, data entries of the top entries of the initiator and target queue do not match, and the initiator queue has more than one entry, determining whether an entry address of a next entry in the initiator queue matches the entry address of the top entry in the initiator queue, and when the entry addresses of the next entry and the top entry in the initiator queue match, merging the top and next entry of the initiator queue and deleting the top entry of initiator queue.
    Type: Application
    Filed: May 22, 2018
    Publication date: November 28, 2019
    Inventor: PRAKASHKUMAR GOVINDBHAI MAKWANA