Patents by Inventor Prasad Padmanabhan
Prasad Padmanabhan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088237Abstract: In an example, a semiconductor device includes an active trench region and an intersecting trench. The active region includes an active shield electrode and the intersecting trench includes an intersecting shield electrode. A coupling trench region connects the active trench region to the intersecting trench region. The coupling trench region includes a coupling shield electrode. The coupling shield electrode and the intersecting shield electrode are provided proximate to a termination mesa region. One or more of the coupling shield electrode or the intersecting shield electrode is thinner than the active shield electrode. The thinner shield electrode reduces depletion in the termination mesa region to improve, among other things, breakdown voltage performance.Type: ApplicationFiled: August 23, 2023Publication date: March 14, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Balaji PADMANABHAN, Prasad VENKATRAMAN
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Patent number: 7130716Abstract: A system for wafer handling employing a complex numerical method for calculating a path of wafer travel that controls wafer acceleration and jerk, and results in maximum safe speed of wafer movement from a first point to a second point. Motion is begun along a straight line segment while accelerating to a first path velocity. During this acceleration, the system computer calculates a series of straight line segments and interconnecting sinusiodally shaped paths over which the wafer is to be guided to the second point. The straight line segments and sinusiodally shaped paths are calculated so as to minimize total path length and the time required to move the wafer from the first point to the second point. The system computes the point of entrance and exit to and from each straight and sinusoidal path.Type: GrantFiled: April 22, 2004Date of Patent: October 31, 2006Assignee: Berkeley Process Control, Inc.Inventors: John Rogers, Prasad Padmanabhan, Paul Sagues
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Publication number: 20040249509Abstract: A system for wafer handling employing a complex numerical method for calculating a path of wafer travel that controls wafer acceleration and jerk, and results in maximum safe speed of wafer movement from a first point to a second point. Motion is begun along a straight line segment while accelerating to a first path velocity. During this acceleration, the system computer calculates a series of straight line segments and interconnecting sinusiodally shaped paths over which the wafer is to be guided to the second point. The straight line segments and sinusiodally shaped paths are calculated so as to minimize total path length and the time required to move the wafer from the first point to the second point. The system computes the point of entrance and exit to and from each straight and sinusoidal path.Type: ApplicationFiled: April 22, 2004Publication date: December 9, 2004Inventors: John Rogers, Prasad Padmanabhan, Paul Sagues
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Patent number: 6736927Abstract: A system is disclosed for speeding workpiece thoughput in low pressure, high temperature semiconductor processing reactor. The system includes apparatus for loading a workpiece into a chamber at atmospheric pressure, bringing the chamber down to an intermediate pressure, and heating the wafer while under the intermediate pressure. The chamber is then pumped down to the operating pressure. The preferred embodiments involve single wafer plasma ashers, where a wafer is loaded onto lift pins at a position above a wafer chuck, the pressure is rapidly pumped down to about 40 Torr by rapidly opening and closing an isolation valve, and the wafer is simultaneously lowered to the heated chuck. Alternatively, the wafer can be pre-processed to remove an implanted photoresist crust at a first temperature and the chamber then backfilled to about 40 Torr for further heating to close to the chuck temperature.Type: GrantFiled: June 10, 2002Date of Patent: May 18, 2004Assignee: Matrix Integrated Systems, Inc.Inventors: Albert Wang, Scott Baron, Prasad Padmanabhan, Gerald M. Cox
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Patent number: 6605226Abstract: A method is disclosed for speeding workpiece thoughput in low pressure, high temperature semiconductor processing reactor. The method includes loading a workpiece into a chamber at atmospheric pressure, bringing the chamber down to an intermediate pressure, and heating the wafer while under the intermediate pressure. The chamber is then pumped down to the operating pressure. The preferred embodiments involve single wafer plasma ashers, where a wafer is loaded onto lift pins at a position above a wafer chuck, the pressure is rapidly pumped down to about 40 Torr by rapidly opening and closing an isolation valve, and the wafer is simultaneously lowered to the heated chuck. Alternatively, the wafer can be pre-processed to remove an implanted photoresist crust at a first temperature and the chamber then backfilled to about 40 Torr for further heating to close to the chuck temperature. At 40 Torr, the heat transfer from the chuck to the wafer is relatively fast, but still slow enough to avoid thermal shock.Type: GrantFiled: June 10, 2002Date of Patent: August 12, 2003Assignee: Matrix Integrated Systems, Inc.Inventors: Albert Wang, Scott Baron, Prasad Padmanabhan, Gerald M. Cox
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Publication number: 20020153099Abstract: A system is disclosed for speeding workpiece thoughput in low pressure, high temperature semiconductor processing reactor. The system includes apparatus for loading a workpiece into a chamber at atmospheric pressure, bringing the chamber down to an intermediate pressure, and heating the wafer while under the intermediate pressure. The chamber is then pumped down to the operating pressure. The preferred embodiments involve single wafer plasma ashers, where a wafer is loaded onto lift pins at a position above a wafer chuck, the pressure is rapidly pumped down to about 40 Torr by rapidly opening and closing an isolation valve, and the wafer is simultaneously lowered to the heated chuck. Alternatively, the wafer can be pre-processed to remove an implanted photoresist crust at a first temperature and the chamber then backfilled to about 40 Torr for further heating to close to the chuck temperature.Type: ApplicationFiled: June 10, 2002Publication date: October 24, 2002Inventors: Albert Wang, Scott Baron, Prasad Padmanabhan, Gerald M. Cox
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Publication number: 20020151184Abstract: A method is disclosed for speeding workpiece thoughput in low pressure, high temperature semiconductor processing reactor. The method includes loading a workpiece into a chamber at atmospheric pressure, bringing the chamber down to an intermediate pressure, and heating the wafer while under the intermediate pressure. The chamber is then pumped down to the operating pressure. The preferred embodiments involve single wafer plasma ashers, where a wafer is loaded onto lift pins at a position above a wafer chuck, the pressure is rapidly pumped down to about 40 Torr by rapidly opening and closing an isolation valve, and the wafer is simultaneously lowered to the heated chuck. Alternatively, the wafer can be pre-processed to remove an implanted photoresist crust at a first temperature and the chamber then backfilled to about 40 Torr for further heating to close to the chuck temperature. At 40 Torr, the heat transfer from the chuck to the wafer is relatively fast, but still slow enough to avoid thermal shock.Type: ApplicationFiled: June 10, 2002Publication date: October 17, 2002Inventors: Albert Wang, Scott Baron, Prasad Padmanabhan, Gerald M. Cox
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Patent number: 6409932Abstract: A method is disclosed for speeding workpiece thoughput in low pressure, high temperature semiconductor processing reactor. The method includes loading a workpiece into a chamber at atmospheric pressure, bringing the chamber down to an intermediate pressure, and heating the wafer while under the intermediate pressure. The chamber is then pumped down to the operating pressure. The preferred embodiments involve single wafer plasma ashers, where a wafer is loaded onto lift pins at a position above a wafer chuck, the pressure is rapidly pumped down to about 40 Torr by rapidly opening and closing an isolation valve, and the wafer is simultaneously lowered to the heated chuck. Alternatively, the wafer can be pre-processed to remove an implanted photoresist crust at a first temperature and the chamber then backfilled to about 40 Torr for further heating to close to the chuck temperature. At 40 Torr, the heat transfer from the chuck to the wafer is relatively fast, but still slow enough to avoid thermal shock.Type: GrantFiled: December 27, 2000Date of Patent: June 25, 2002Assignee: Matrix Integrated Systems, Inc.Inventors: Albert Wang, Scott Baron, Prasad Padmanabhan, Gerald M. Cox
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Publication number: 20010047979Abstract: A method is disclosed for speeding workpiece thoughput in low pressure, high temperature semiconductor processing reactor. The method includes loading a workpiece into a chamber at atmospheric pressure, bringing the chamber down to an intermediate pressure, and heating the wafer while under the intermediate pressure. The chamber is then pumped down to the operating pressure. The preferred embodiments involve single wafer plasma ashers, where a wafer is loaded onto lift pins at a position above a wafer chuck, the pressure is rapidly pumped down to about 40 Torr by rapidly opening and closing an isolation valve, and the wafer is simultaneously lowered to the heated chuck. Alternatively, the wafer can be pre-processed to remove an implanted photoresist crust at a first temperature and the chamber then backfilled to about 40 Torr for further heating to close to the chuck temperature. At 40 Torr, the heat transfer from the chuck to the wafer is relatively fast, but still slow enough to avoid thermal shock.Type: ApplicationFiled: December 27, 2000Publication date: December 6, 2001Inventors: Albert Wang, Scott Baron, Prasad Padmanabhan
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Patent number: 6175698Abstract: The present invention generally relates to an imaging system, and more specifically, a method and apparatus for accurately predicting toner usage and hence toner dispensing requirements in an imaging system. The toner concentration control system maintains toner concentration in a developer structure, which is connected to a dispenser containing toner.Type: GrantFiled: October 27, 1999Date of Patent: January 16, 2001Assignee: Xerox CorporationInventors: Mark A. Scheuer, John Buranicz, Patricia J. Donaldson, Paul A. Garsin, Eric M. Gross, Eric S. Hamby, Daniel W. MacDonald, Prasad Padmanabhan, Edward W. Smith, Jr., Joseph W. Ward
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Patent number: 6167214Abstract: The present invention generally relates to an imaging system, and more specifically, a method and apparatus for accurately predicting toner usage and hence toner dispensing requirements in an imaging system. More specifically, the present invention relates to a feed forward toner concentration control system and method for replacing toner in each developer structure, which was used to develop a latent image on a photoreceptor belt, in order to maintain toner concentration in at least one developer structure. First and second pixel counts for first and second toner in each sector are received. The first toner mass is estimated based on first pixel counts. The second toner mass is estimated based on second pixel counts.Type: GrantFiled: October 27, 1999Date of Patent: December 26, 2000Assignee: Xerox CorporationInventors: Mark A. Scheuer, Prasad Padmanabhan, Joseph W. Ward
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Patent number: 6160971Abstract: The present invention generally relates to an imaging system, and more specifically, a method and apparatus for accurately predicting toner usage and hence toner dispensing requirements in an imaging system. More specifically, the present invention relates to a toner concentration control system for maintaining toner concentration in a developer structure, which is connected to a dispenser containing toner.Type: GrantFiled: October 27, 1999Date of Patent: December 12, 2000Assignee: Xerox CorporationInventors: Mark A. Scheuer, John Buranicz, Patricia J. Donaldson, Paul A. Garsin, Eric M. Gross, Eric S. Hamby, Daniel W. MacDonald, Prasad Padmanabhan, Edward W. Smith, Jr., Joseph W. Ward
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Patent number: 5754918Abstract: An electrostatographic printing machine having an imaging member with a surface voltage potential and a control system including first and second reference values. A sensor measures first and second surface voltage potentials that are compared to the first and second reference values to provide first and second error signals to control first and second process stations in the printing machine. A first compensator responds to the first error signal to provide a first weighted adjustment to the first process station and a second weighted adjustment to the second process station. A second compensator responds to the second error signal to provide a first weighted adjustment to the second process station and a second weighted adjustment to the first process station in order to compensate for coupling effects between adjustments to either the first or second processing stations.Type: GrantFiled: December 4, 1996Date of Patent: May 19, 1998Assignee: Xerox CorporationInventors: Lingappa K. Mestha, Prasad Padmanabhan