Abstract: An automated routing tool for routing interconnections between circuit elements, standard cells and/or cell blocks of cell-based designs which incorporates the best features of both currently known gate array routing techniques with currently known cell-based routing techniques. The invention eliminates the disadvantages of permitting the detailed router to adjust the relative positions of the circuit elements, standard cells and/or cell blocks during the detailed routing process. The method employs a topology manager which iteratively compacts the circuit topology while at the same time optimizing the routing of the interconnections among the circuit elements, standard cells and/or cell blocks of the circuit design. The method employs bin-based global routing, which identifies expandable boundaries and which provides input to a compaction routine which expands or contracts the expandable areas in accordance with the result of the global routing process.

Abstract: In a method for providing routing between logic cells, the logic cells are arranged in rows. Intercell connectors within each row of logic cells are aligned, for example in the middle of the rows, to form channel boundaries. The intercell connectors are then channel routed in metal layers above the logic cells. Alternately, intercell connectors are placed within the logic cells, however, these intercell connectors are not necessarily aligned. For each intercell connector which is not on a boundary of a routing channel, a substitute connector is located at the boundary of a routing channel. The substitute connectors and the intercell connectors which are on the boundaries of the routing channels are channel routed. Length of routing segments are then adjusted to substitute connectors to extend to intercell connectors instead of the substitute connectors.