Patents by Inventor Prasad Sarangapani

Prasad Sarangapani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11372948
    Abstract: A non-transitory machine-readable storage medium is disclosed, which stores a program for modeling a many particle system. When executed on a processing system, the program causes the processing system to (1) determine a compensation function that, when applied to a plurality of interaction equations, compensates for errors introduced by an approximation included in at least one of the plurality of interaction equations, (2) determine an uncompensated solution of the many particle system by solving the many particle system without the plurality of interaction equations, (3) calculate a plurality of observables in the many particle system by solving the many particle system with the plurality of interaction equations by a first iteration, and (4) model the many particle system based on the plurality of observables.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: June 28, 2022
    Assignee: Purdue Research Foundation
    Inventors: Tillmann Kubis, Prasad Sarangapani
  • Patent number: 10763367
    Abstract: A tunnel field-effect transistor (TFET) includes a fin, an insulator layer, and at least one gate. The fin has a doped first region, a doped second region, and an interior region between the first region and the second region. The interior region is undoped or is more lightly doped than the first region and the second region. At least the interior region of the fin formed as a type II superlattice, wherein materials of the superlattice alternate vertically. The insulator layer is formed around the interior region. The gate is formed on at least a portion of the insulator region. The insulator layer and the at least one gate are configured to generate an inhomogeneous electrostatic potential within the interior region.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: September 1, 2020
    Assignee: Purdue Research Foundation
    Inventors: Tillmann C. Kubis, Prasad Sarangapani
  • Publication number: 20200159807
    Abstract: A non-transitory machine readable storage medium having a machine readable program stored therein, wherein the machine readable program, when executed on a processing system, causes the processing system to perform a method of modeling a many particle system, wherein the method includes determining a compensation function, wherein the compensation function compensates errors introduced by an approximation of at least one of a plurality of interaction equations applied on the plurality of interaction equations, wherein the plurality of interaction equations includes the approximation. The method additionally includes solving at least a system of the many particle system without the plurality of interaction equations to extract an uncompensated solution of the many particle system.
    Type: Application
    Filed: November 15, 2019
    Publication date: May 21, 2020
    Applicant: Purdue Research Foundation
    Inventors: Tillmann Kubis, Prasad Sarangapani
  • Publication number: 20190348536
    Abstract: A tunnel field-effect transistor (TFET) includes a fin, an insulator layer, and at least one gate. The fin has a doped first region, a doped second region, and an interior region between the first region and the second region. The interior region is undoped or is more lightly doped than the first region and the second region. At least the interior region of the fin formed as a type II superlattice, wherein materials of the superlattice alternate vertically. The insulator layer is formed around the interior region. The gate is formed on at least a portion of the insulator region. The insulator layer and the at least one gate are configured to generate an inhomogeneous electrostatic potential within the interior region.
    Type: Application
    Filed: May 9, 2019
    Publication date: November 14, 2019
    Inventors: Tillmann C. Kubis, Prasad Sarangapani
  • Patent number: 7466194
    Abstract: An amplifier is described which includes a first loop including a first amplifier stage having an offset voltage associated therewith. An output stage includes two switching devices in a bridge configuration configured to be coupled between a supply voltage and ground. An output of the bridge configuration is configured to be coupled to a load. The first loop is characterized by a first gain. A decoupling capacitor is configured to be coupled to the load. A second loop which includes the first amplifier stage is configured to charge the decoupling capacitor to a first voltage generated with reference to the offset voltage before operation of the switching devices is enabled. The second loop is characterized by a second gain. The first and second gains are substantially the same such that when operation of the switching devices is enabled a second voltage at the output of the half-bridge configuration is substantially the same as the first voltage.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: December 16, 2008
    Assignee: Cirrus Logic, Inc.
    Inventors: Babak Mazda, Rahul Shinkre, Farzad Sahandiesfanjani, Maziar Sayyedi, Krishna Prasad Sarangapani