Abstract: A half-bridge circuit can include a high-side HEMT, a high-side switch transistor, a low-side HEMT, and a low-side switch transistor. The die substrates of the HEMTs can be coupled to the sources of their corresponding switch transistors. In another aspect, a packaged electronic device for a half-bridge circuit can have a design that can use shorter connectors that help to reduce parasitic inductance and resistance. In a further aspect, a packaged electronic device for a half-bridge circuit can include more than one connection along the bottom of the package allows less lead connections along the periphery of the packaged electronic device and can allow for a smaller package.

Abstract: In one embodiment, a group III-V transistor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A clamping device is integrated with the group III-V transistor structure and is electrically connected to the first current carrying electrode a third electrode to provide a secondary current path during, for example, an electrical stress event.

Abstract: In one embodiment, a cascode rectifier structure includes a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A rectifier device is integrated with the group III-V semiconductor structure and is electrically connected to the first current carrying electrode and to a third electrode. The control electrode is further electrically connected to the semiconductor substrate and the second current path is generally perpendicular to a primary current path between the first and second current carrying electrodes.

Abstract: In accordance with an embodiment, a semiconductor component includes a support having first and second device receiving structures. A semiconductor device configured from a III-N semiconductor material is coupled to the support, wherein the semiconductor device has opposing surfaces. A first bond pad extends from a first portion of the first surface, a second bond pad extends from a second portion of the first surface, and a third bond pad extends from a third portion of the first surface. The first bond pad is coupled to the first device receiving portion, the drain bond pad is coupled to the second device receiving portion, and the third bond pad is coupled to the third lead. In accordance with another embodiment, a method includes coupling a semiconductor chip comprising a III-N semiconductor substrate material to a support.

Abstract: Embodiments include a method and structure to that provide a clamping structure in an integrated semiconductor device. In accordance with an embodiment, the method includes forming trenches in a semiconductor material and forming a shield electrode in a portion of at least one of the trenches. A clamping structure is formed adjacent to a trench. The clamping structure has an electrode that may be electrically connected to a source region of the integrated semiconductor device. In accordance with another embodiment, an impedance element is formed in a trench.

Abstract: An electronic device can include a bidirectional HEMT. In an aspect, a packaged electronic device can include the bidirectional HEMT can be part of a die having a die substrate connection that is configured to be at a fixed voltage, electrically connected to drain/source or source/drain depending on current flow through the bidirectional HEMT, or electrically float. In another aspect, the electronic device can include Kelvin connections on both the drain/source and source/drain side of the circuit. In a further embodiment, a circuit can include the bidirectional HEMT, switch transistors, and diodes with breakdown voltages to limit voltage swings at the drain/source and source/drain of the switch transistors.

Abstract: In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure, a second device receiving structure, a first lead, a second lead, and a third lead. A first semiconductor chip is coupled to the first device receiving structure and a second semiconductor chip is coupled to the first semiconductor chip and the second device receiving structure. The first semiconductor chip is configured from a silicon semiconductor material and has a gate bond pad, a source bond pad, and a drain bond pad, and the second semiconductor chip is configured from a gallium nitride semiconductor chip and has a gate bond pad, a source bond pad, and a drain bond pad. In accordance with another embodiment, a method for manufacturing a semiconductor component includes coupling a first semiconductor chip to a support and coupling a second semiconductor chip to the support.

Abstract: In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure, a second device receiving structure, a first lead and a second lead. A first semiconductor chip is coupled to the first device receiving structure and a second semiconductor chip is coupled to the first semiconductor chip and the second device receiving structure. The first semiconductor chip is configured from a silicon semiconductor material and has a gate bond pad, a source bond pad, and a drain bond pad, and the second semiconductor chip is configured from a gallium nitride semiconductor chip and has a gate bond pad, a source bond pad, and a drain bond pad. In accordance with another embodiment, a method for manufacturing a semiconductor component includes coupling a first semiconductor chip to a support and coupling a second semiconductor chip to the support.

Abstract: In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure, a second device receiving structure, a first lead and a second lead. A first semiconductor chip is coupled to the first device receiving structure and a second semiconductor chip is coupled to the first semiconductor chip and the second device receiving structure. The first semiconductor chip is configured from a silicon semiconductor material and has a gate bond pad, a source bond pad, and a drain bond pad, and the second semiconductor chip is configured from a gallium nitride semiconductor chip and has a gate bond pad, a source bond pad, and a drain bond pad. In accordance with another embodiment, a method for manufacturing a semiconductor component includes coupling a first semiconductor chip to a support and coupling a second semiconductor chip to the support.

Abstract: In accordance with an embodiment, a cascode connected semiconductor component and a method for manufacturing the cascode connected semiconductor component are provided. The cascode connected semiconductor component has a pair of silicon based transistors, each having a body region, a gate region over the body region, a source region and a drain. The source regions of a first and second silicon based transistor are electrically connected together and the drain regions of the first and second silicon based transistors are electrically connected together. The gate region of the second silicon based transistor is connected to the drain regions of the first and second silicon based transistors. The body region of the second silicon based transistor has a dopant concentration that is greater than the dopant concentration of the first silicon based transistor. A gallium nitride based transistor has a source region coupled to the first and second silicon based transistor.

Abstract: In accordance with an embodiment, a semiconductor component includes a support and a plurality of leads. An insulated metal substrate having a first portion and a second portion bonded to the support. A semiconductor chip comprising a III-N semiconductor material is bonded to the first portion of the insulated metal substrate and a first electrical interconnect is coupled between a drain bond pad the first portion of the insulated metal substrate. A second semiconductor chip is bonded to the first electrical interconnect. A second electrical interconnect coupled between a lead of the plurality of leads and the second semiconductor chip. In accordance with another embodiment, a method of manufacturing a semiconductor component includes coupling a first semiconductor chip to a first electrically conductive layer and coupling a second semiconductor chip to a second electrically conductive layer.

Abstract: In accordance with an embodiment, a semiconductor component includes a support having first and second device receiving structures. A semiconductor device configured from a III-N semiconductor material is coupled to the support, wherein the semiconductor device has opposing surfaces. A first bond pad extends from a first portion of the first surface, a second bond pad extends from a second portion of the first surface, and a third bond pad extends from a third portion of the first surface. The first bond pad is coupled to the first device receiving portion, the drain bond pad is coupled to the second device receiving portion, and the third bond pad is coupled to the third lead. In accordance with another embodiment, a method includes coupling a semiconductor chip comprising a III-N semiconductor substrate material to a support.

Abstract: In accordance with an embodiment, a semiconductor component includes a support having first and second device receiving structures. A semiconductor device configured from a III-N semiconductor material is coupled to the support, wherein the semiconductor device has opposing surfaces. A first bond pad extends from a first portion of the first surface, a second bond pad extends from a second portion of the first surface, and a third bond pad extends from a third portion of the first surface. The first bond pad is coupled to the first device receiving portion, the drain bond pad is coupled to the second device receiving portion, and the third bond pad is coupled to the third lead. In accordance with another embodiment, a method includes coupling a semiconductor chip comprising a III-N semiconductor substrate material to a support.

Abstract: In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure, a second device receiving structure, a first lead, a second lead, and a third lead. A first semiconductor chip is coupled to the first device receiving structure and a second semiconductor chip is coupled to the first semiconductor chip and the second device receiving structure. The first semiconductor chip is configured from a silicon semiconductor material and has a gate bond pad, a source bond pad, and a drain bond pad, and the second semiconductor chip is configured from a gallium nitride semiconductor chip and has a gate bond pad, a source bond pad, and a drain bond pad. In accordance with another embodiment, a method for manufacturing a semiconductor component includes coupling a first semiconductor chip to a support and coupling a second semiconductor chip to the support.

Abstract: In accordance with an embodiment, semiconductor component having a compound semiconductor material based semiconductor device connected to a silicon based semiconductor device and a protection element, wherein the silicon based semiconductor device is a transistor. The protection element is coupled in parallel across the silicon based semiconductor device and may be a resistor, a diode, or a transistor. In accordance with another embodiment, the silicon based semiconductor device is a diode. The compound semiconductor material may be shorted to a source of potential such as, for example, ground, with a shorting element.

Abstract: In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure and a second device receiving structure and a contact extension that is common to the first and second device receiving structures. The first device receiving structure includes a device receiving area and the second device receiving structure includes a drain contact area. A III-N based semiconductor chip has a drain bond pad bonded to the drain contact area and a source bond pad bonded to the contact extension and a gate bond pad bonded to an interconnect. A portion of the silicon based semiconductor chip is bonded to the support device receiving area. In accordance with another embodiment, a method for manufacturing the semiconductor component includes coupling a III-N based semiconductor chip to a portion of the support a silicon based semiconductor chip to another portion of the support.

Abstract: In one embodiment, a semiconductor device is formed to include a gate structure extending into a semiconductor material that is underlying a first region of semiconductor material. The gate structure includes a conductor and also a gate insulator that has a first portion positioned between the gate conductor and a first portion of the semiconductor material that underlies the gate conductor. The first portion of the semiconductor material is configured to form a channel region of the transistor which underlies the gate conductor. The gate structure may also include a shield conductor overlying the gate conductor and having a shield insulator between the shield conductor and the gate conductor. The shield insulator may also have a second portion positioned between the shield conductor and a second portion of the gate insulator and a third portion overlying the shield conductor.

Abstract: In one embodiment, Group III-nitride materials are used to form a semiconductor device. A fin structure is formed in the Group III-nitride material, and a gate structure, source electrodes and drain electrodes are formed in spaced relationship to the fin structure. The fin structure provides both polar and semi-polar 2DEG regions. In one embodiment, the gate structure is configured to control current flow in the polar 2DEG region. Shield conductor layers are included above the gate structure and in spaced relationship with drain regions of the semiconductor device.

Abstract: An electronic device can include a bidirectional HEMT. In an aspect, a packaged electronic device can include the bidirectional HEMT can be part of a die having a die substrate connection that is configured to be at a fixed voltage, electrically connected to drain/source or source/drain depending on current flow through the bidirectional HEMT, or electrically float. In another aspect, the electronic device can include Kelvin connections on both the drain/source and source/drain side of the circuit. In a further embodiment, a circuit can include the bidirectional HEMT, switch transistors, and diodes with breakdown voltages to limit voltage swings at the drain/source and source/drain of the switch transistors.

Abstract: A half-bridge circuit can include a high-side HEMT, a high-side switch transistor, a low-side HEMT, and a low-side switch transistor. The die substrates of the HEMTs can be coupled to the sources of their corresponding switch transistors. In another aspect, a packaged electronic device for a half-bridge circuit can have a design that can use shorter connectors that help to reduce parasitic inductance and resistance. In a further aspect, a packaged electronic device for a half-bridge circuit can include more than one connection along the bottom of the package allows less lead connections along the periphery of the packaged electronic device and can allow for a smaller package.