Patents by Inventor Prasanna Raghavan

Prasanna Raghavan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230307379
    Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate, and a die coupled to the package substrate. In an embodiment, the electronic package further comprises a stiffener on the package substrate surrounding the die. In an embodiment, the stiffener is a ring with one or more corner regions and one or more beams. In an embodiment, each beam is between a pair of corner regions, and the one or more corner regions have a first thickness and the one or more beams have a second thickness that is greater than the first thickness.
    Type: Application
    Filed: March 24, 2022
    Publication date: September 28, 2023
    Inventors: Phil GENG, Patrick NARDI, Ravindranath V. MAHAJAN, Dingying David XU, Prasanna RAGHAVAN, John HARPER, Sanjoy SAHA, Yang JIAO
  • Patent number: 11322456
    Abstract: A foundation layer having a stiffener and methods of forming a stiffener are described. One or more dies are formed over the foundation layer. Each die has a front side surface that is electrically coupled to the foundation layer and a back side surface that is opposite from the front side surface. A stiffening layer (or a stiffener) is formed on the back side surface of at least one of the dies. The stiffening layer may be directly coupled to the back side surface of the one or more dies without an adhesive layer. The stiffening layer may include one or more materials, including at least one of a metal, a metal alloy, and a ceramic. The stiffening layer may be formed to reduce warpage based on the foundation layer and the dies. The one or more materials of the stiffening layer can be formed using a cold spray.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: Feras Eid, Venkata Suresh R. Guthikonda, Shankar Devasenathipathy, Chandra M. Jha, Je-Young Chang, Kyle Yazzie, Prasanna Raghavan, Pramod Malatkar
  • Patent number: 10845552
    Abstract: An optoelectronic apparatus is presented. In embodiments, the apparatus may include a package including a substrate with a first side and a second side opposite the first side, wherein the first side comprises a ball grid array (BGA) field. The apparatus may further include one or more integrated circuits (ICs) disposed on the first side of the substrate, inside the BGA field, that thermally interface with a printed circuit board (PCB), to which the package is to be coupled, one or more optical ICs coupled to the second side and communicatively coupled with the one or more ICs via interconnects provided in the substrate, wherein at least one of the optical ICs is at least partially covered by an integrated heat spreader (IHS), to provide dissipation of heat produced by the at least one optical IC.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Shawna M. Liff, Henning Braunisch, Timothy A. Gosselin, Prasanna Raghavan, Yikang Deng, Zhiguo Qian
  • Publication number: 20200066655
    Abstract: A foundation layer having a stiffener and methods of forming a stiffener are described. One or more dies are formed over the foundation layer. Each die has a front side surface that is electrically coupled to the foundation layer and a back side surface that is opposite from the front side surface. A stiffening layer (or a stiffener) is formed on the back side surface of at least one of the dies. The stiffening layer may be directly coupled to the back side surface of the one or more dies without an adhesive layer. The stiffening layer may include one or more materials, including at least one of a metal, a metal alloy, and a ceramic. The stiffening layer may be formed to reduce warpage based on the foundation layer and the dies. The one or more materials of the stiffening layer can be formed using a cold spray.
    Type: Application
    Filed: June 30, 2017
    Publication date: February 27, 2020
    Inventors: Feras EID, Venkata Suresh R. GUTHIKONDA, Shankar DEVASENATHIPATHY, Chandra M. JHA, Je-Young CHANG, Kyle YAZZIE, Prasanna RAGHAVAN, Pramod MALATKAR
  • Publication number: 20190317285
    Abstract: An optoelectronic apparatus is presented. In embodiments, the apparatus may include a package including a substrate with a first side and a second side opposite the first side, wherein the first side comprises a ball grid array (BGA) field. The apparatus may further include one or more integrated circuits (ICs) disposed on the first side of the substrate, inside the BGA field, that thermally interface with a printed circuit board (PCB), to which the package is to be coupled, one or more optical ICs coupled to the second side and communicatively coupled with the one or more ICs via interconnects provided in the substrate, wherein at least one of the optical ICs is at least partially covered by an integrated heat spreader (IHS), to provide dissipation of heat produced by the at least one optical IC.
    Type: Application
    Filed: September 12, 2017
    Publication date: October 17, 2019
    Inventors: Shawna M. LIFF, Henning BRAUNISCH, Timothy A. GOSSELIN, Prasanna RAGHAVAN, Yikang DENG, Zhiguo QIAN
  • Patent number: 10231338
    Abstract: Methods of forming a package structures comprising a trench are described. An embodiment includes a first die disposed on a first substrate, and at least one interconnect structure disposed on a peripheral region of the first substrate. A molding compound is disposed on a portion of the first substrate and on the first die, wherein a trench opening is disposed in the molding compound that is located between the at least one interconnect structure and the first die.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: March 12, 2019
    Assignee: INTEL CORPORATION
    Inventors: Naga Sivakumar Yagnamurthy, Huiyang Fei, Pramod Malatkar, Prasanna Raghavan, Robert Nickerson
  • Patent number: 9633937
    Abstract: The electronic package includes a substrate and an electronic component mounted to a surface of the substrate. An interposer is mounted to the surface of the substrate such that the interposer surrounds the electronic component and is electrically connected to the substrate. An over-mold covers the electronic component. In other forms, the example electronic package may be incorporated into an electronic assembly. The electronic assembly further includes a second electronic component mounted to the interposer. As an example, the second electronic component may be mounted to the interposer using solder bumps. It should be noted that any technique that is known now, or discovered in the future, may be used to mount the second electronic component to the interposer.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 25, 2017
    Assignee: Intel Corporation
    Inventors: Huiyang Fei, Prasanna Raghavan
  • Publication number: 20160381800
    Abstract: Methods of forming a package structures comprising a trench are described. An embodiment includes a first die disposed on a first substrate, and at least one interconnect structure disposed on a peripheral region of the first substrate. A molding compound is disposed on a portion of the first substrate and on the first die, wherein a trench opening is disposed in the molding compound that is located between the at least one interconnect structure and the first die.
    Type: Application
    Filed: June 24, 2015
    Publication date: December 29, 2016
    Inventors: Naga Sivakumar Yagnamurthy, Huiyang Fei, Pramod Malatkar, Prasanna Raghavan, Robert Nickerson
  • Publication number: 20160225707
    Abstract: The electronic package includes a substrate and an electronic component mounted to a surface of the substrate. An interposer is mounted to the surface of the substrate such that the interposer surrounds the electronic component and is electrically connected to the substrate. An over-mold covers the electronic component. In other forms, the example electronic package may be incorporated into an electronic assembly. The electronic assembly further includes a second electronic component mounted to the interposer. As an example, the second electronic component may be mounted to the interposer using solder bumps. It should be noted that any technique that is known now, or discovered in the future, may be used to mount the second electronic component to the interposer.
    Type: Application
    Filed: December 16, 2014
    Publication date: August 4, 2016
    Inventors: Huiyang FEI, Prasanna RAGHAVAN
  • Publication number: 20070152314
    Abstract: A stacked die package comprises a first die on a substrate, a die attach layer superjacent to the first die, and a second die on the die attach layer. The die attach layer comprises a die attach material having a glass transition temperature substantially in the range of 150-180° C. Raising the glass transition temperature reduces the mismatch in the coefficients of thermal expansion (CTE) between the die attach and the mold compound that surrounds the first die in the package.
    Type: Application
    Filed: December 30, 2005
    Publication date: July 5, 2007
    Inventors: Rahul Manepalli, Amram Eitan, Prasanna Raghavan