Abstract: A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information; and overwriting the existing frame of configuration information in the configuration memory array with the modified frame, thereby partially reconfiguring the IC.

Abstract: A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information; and overwriting the existing frame of configuration information in the configuration memory array with the modified frame, thereby partially reconfiguring the IC.

Abstract: A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information; and overwriting the existing frame of configuration information in the configuration memory array with the modified frame, thereby partially reconfiguring the IC.

Abstract: Method and system for testing circuitry of a programmable logic device (PLD). A host data processing arrangement is configured with a run-time reconfiguration programming interface, and a run-time reconfiguration test program that invokes methods of the interface executes on the host arrangement. In response to a method of the programming interface invoked from the test program, the PLD is configured with a first configuration bitstream. State data are then read back from the PLD in response to a method of the programming interface invoked from the test program. The test program also identifies differences between the state data and expected-results data.

Abstract: An adaptable configuration interface for a programmable logic device (PLD). A PLD includes a plurality of configuration pins and circuitry implementing read and write protocols for reading data from and writing configuration data to the PLD. A register that is external to the PLD is connected to the configuration pins of the PLD, and a processor is coupled to the register. A first set of routines, each executable on the processor, are configured to read and write values from and to the register. A second set of routines, each executable on the processor, provide an application programming interface for the configuration and readback of data from the PLD via the first set of routines. The layered structure of the interface routines aids in incrementally changing from a software controlled configuration interface to an interface that is a combination of hardware and software.

Abstract: Method and apparatus for tolerating defects in a programmable logic device (PLD). A PLD includes a plurality of configurable logic elements and interconnect resources, wherein one or more of the configurable logic elements and interconnect resources have circuit defects. A design program is executed that is suitable for run-time reconfiguration of the PLD. The design program includes executable code that specifies a circuit design and generates a configuration bitstream that implements the circuit design on the programmable logic device. The design program also includes code that selectively skips the configurable logic elements and interconnect resources that contain the defects. In various embodiments, an individual configurable logic element, an entire row, or an entire column of elements can be skipped responsive to an input parameter.