Abstract: Signal paths in a circuit design are identified, and each node in each path to be processed by an electronic design automation operation is assigned a value. More particularly, each node in a signal path to be processed is sequentially assigned an incrementing value. If a node occurring in multiple signal paths already has been assigned a value, and the new value to be assigned to the node is higher than its previously-assigned value, then the node is assigned the higher value. Two or more portions of the circuit design having the same assigned node values are then processed in parallel by the electronic design automation operation.

Abstract: A method and apparatus for identifying potential noise failures in an integrated circuit design is described. In one embodiment, the method comprises locating a victim net and an aggressor within the integrated circuit design, modeling the victim net using two ?-type resistor-capacitor (RC) circuits, including determining a coupling between the victim net and the aggressor, and indicating that the integrated circuit design requires modification if modeling the victim net indicates that a potential noise failure may occur in the integrated circuit design.