Abstract: A mobile consumer device with a display, processor(s), and memory: identifies a merchant device in proximity to the consumer device based on broadcasted information transmitted by the first merchant device, the broadcasted information including a first identifier corresponding to the first merchant device; transmits the first identifier to a server and receives from the server an electronic communication including identification and transaction information associated with the merchant; displays the identification information, receives user selection of the merchant identification information; and in response, displays the merchant transaction information, receives supplemental user information, and transmits the supplemental transaction information to the server for completion of the transaction.

Abstract: A mobile consumer device with a display, processor(s), and memory: identifies a merchant device in proximity to the consumer device based on broadcasted information transmitted by the first merchant device, the broadcasted information including a first identifier corresponding to the first merchant device; transmits the first identifier to a server and receives from the server an electronic communication including identification and transaction information associated with the merchant; displays the identification information, receives user selection of the merchant identification information; and in response, displays the merchant transaction information, receives supplemental user information, and transmits the supplemental transaction information to the server for completion of the transaction.

Abstract: A mobile consumer device with a display, processor(s), and memory: identifies a merchant device in proximity to the consumer device based on broadcasted information transmitted by the first merchant device, the broadcasted information including a first identifier corresponding to the first merchant device; transmits the first identifier to a server and receives from the server an electronic communication including identification and transaction information associated with the merchant; displays the identification information, receives user selection of the merchant identification information; and in response, displays the merchant transaction information, receives supplemental user information, and transmits the supplemental transaction information to the server for completion of the transaction.

Abstract: A mobile consumer device with a display, processor(s), and memory: identifies a merchant device in proximity to the consumer device based on broadcasted information transmitted by the first merchant device, the broadcasted information including a first identifier corresponding to the first merchant device; transmits the first identifier to a server and receives from the server an electronic communication including identification and transaction information associated with the merchant; displays the identification information, receives user selection of the merchant identification information; and in response, displays the merchant transaction information, receives supplemental user information, and transmits the supplemental transaction information to the server for completion of the transaction.

Abstract: An electronic card device includes a Radio Frequency (RF) circuit configured to receive information from a remote broadcast transmitter, a memory associated with the RF circuit to store a unique identifier of the electronic card device, and a processor communicatively coupled to the memory. The processor is configured to enable reception of the information from the remote broadcast transmitter based on the unique identifier of the electronic card device in the memory to generate data configured to facilitate consumer activity on part of a user of the electronic card device through the electronic card device. Also, the electronic card device includes a display unit integrated therewith configured to display output data related to the data generated through the processor.

Abstract: A method for administering transmission of a first type of packets and a second type of packets over a serial bus is disclosed. The method comprises: if there is a packet of a second type to be sent, then concatenating the packet of the second type to a plurality of packets of the first type and sending the plurality of packets of the first type followed by the concatenated packet of the second type; and if there is no packet of the second type to be sent, then concatenating a bogus ack packet to the plurality of packets of the first type and sending the plurality of packets of the first type followed by the concatenated bogus ack packet.

Abstract: A method for administering transmission of a first type of packets and a second type of packets over a serial bus. In one embodiment, the method comprises: if there is a packet of a second type to be sent, then concatenating the packet of the second type to a plurality of packets of the first type and sending the plurality of packets of the first type followed by the concatenated packet of the second type; and if there is no packet of the second type to be sent, then concatenating a bogus ack packet to the plurality of packets of the first type and sending the plurality of packets of the first type followed by the concatenated bogus ack packet.

Abstract: An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead. The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communication station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times.

Abstract: An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead. The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communication station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times.

Abstract: An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead.The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communications station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times.