Patents by Inventor Prasoonkumar B. Surti

Prasoonkumar B. Surti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for fast loading of texture data into a tiled memory
    Patent number: 6496193
    Abstract: An apparatus for loading texture data into a tiled memory includes state machine logic to generate a sequence of addresses for writing a cacheline of texture data into the tiled memory according to Y-major tiling. The cacheline comprises quadwords (QWs) 0-3, wherein the sequence corresponds to an ordering of the QWs 0-3, ordered as either: (a) QW0, QW1, QW2, QW3; (b) QW1, QW0, QW3, QW2; (c) QW2, QW3, QW0, QW1; or (d) QW3, QW2, QW1, QW0, depending upon a starting address.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: December 17, 2002
    Assignee: Intel Corporation
    Inventors: Prasoonkumar B. Surti, Aditya Sreenivas