Patents by Inventor Prasun Gera

Prasun Gera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • 3D-STACKED MEMORY WITH RECONFIGURABLE COMPUTE LOGIC
    Publication number: 20240004547
    Abstract: A 3D-stacked memory device including: a base die including a plurality of switches to direct data flow and a plurality of arithmetic logic units (ALUs) to compute data; a plurality of memory dies stacked on the base die; and an interface to transfer signals to control the base die.
    Type: Application
    Filed: September 15, 2023
    Publication date: January 4, 2024
    Inventors: Mu-Tien Chang, Prasun Gera, Dimin Niu, Hongzhong Zheng
  • 3D-stacked memory with reconfigurable compute logic
    Patent number: 11789610
    Abstract: A 3D-stacked memory device including: a base die including a plurality of switches to direct data flow and a plurality of arithmetic logic units (ALUs) to compute data; a plurality of memory dies stacked on the base die; and an interface to transfer signals to control the base die.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: October 17, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mu-Tien Chang, Prasun Gera, Dimin Niu, Hongzhong Zheng
  • 3D-STACKED MEMORY WITH RECONFIGURABLE COMPUTE LOGIC
    Publication number: 20210311634
    Abstract: A 3D-stacked memory device including: a base die including a plurality of switches to direct data flow and a plurality of arithmetic logic units (ALUs) to compute data; a plurality of memory dies stacked on the base die; and an interface to transfer signals to control the base die.
    Type: Application
    Filed: June 21, 2021
    Publication date: October 7, 2021
    Inventors: Mu-Tien Chang, Prasun Gera, Dimin Niu, Hongzhong Zheng
  • 3-D stacked memory with reconfigurable compute logic
    Patent number: 11079936
    Abstract: A 3D-stacked memory device including: a base die including a plurality of switches to direct data flow and a plurality of arithmetic logic units (ALUs) to compute data; a plurality of memory dies stacked on the base die; and an interface to transfer signals to control the base die.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: August 3, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mu-Tien Chang, Prasun Gera, Dimin Niu, Hongzhong Zheng
  • 3-D STACKED MEMORY WITH RECONFIGURABLE COMPUTE LOGIC
    Publication number: 20170255390
    Abstract: A 3D-stacked memory device including: a base die including a plurality of switches to direct data flow and a plurality of arithmetic logic units (ALUs) to compute data; a plurality of memory dies stacked on the base die; and an interface to transfer signals to control the base die.
    Type: Application
    Filed: April 29, 2016
    Publication date: September 7, 2017
    Inventors: Mu-Tien Chang, Prasun Gera, Dimin Niu, Hongzhong Zheng