Abstract: A system includes a synchronizer circuit configured to monitor a first bus coupled between a memory and a first device to determine an occupancy threshold of the memory based on one or more write requests from the first device. The synchronizer circuit monitors a second bus between the memory and a second device to receive a first read transaction of a read request from the second device. The synchronizer circuit determines that the first read transaction is allowed to be sent to the memory based on the occupancy threshold of the memory. In response to the determination, the first read transaction is sent to the memory.

Abstract: A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.

Abstract: A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.

Abstract: A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.

Abstract: A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.

Abstract: A method and apparatus for a multiple lane transmission system that provides both a low latency mode of operation, while at the same time, provides reduced lane-lane skew. The overall transmission system operates as a mesochronous system, whereby each clock domain of the transmission system is synchronized to the leaf nodes of a global clock tree. A phase aligner is then used to align the phase of both the bit and byte clocks of each transmission lane to the clock signal generated at the leaf nodes of the global clock tree.

Abstract: A method and apparatus for a receive equalizer of a gigabit transceiver that is reconfigurable to support multiple communication standards. Communication standards having variable common mode and coupling requirements are accommodated through the use of reconfigurable integrated circuits (ICs), such as field programmable gate arrays (FPGAs), that provide a plurality of reconfigurable transceivers that are programmable through configuration, or partial reconfiguration, events. The reconfigurable transceivers apply internally generated common mode voltage signals to the differential input in support of the various communication standards.

Abstract: In one embodiment, a system for frequency and phase correction in a phase-locked loop (PLL) includes a phase frequency detector, first and second charge pumps respectively generating a first current and a voltage, a voltage-to-current (V2I) converter, a current summer, and a current-controlled oscillator (CCO). The phase frequency detector detects a frequency difference and a phase difference between a clock signal and a comparison signal, communicates the frequency difference to a first charge pump generating a first current, and communicates the phase difference to a second charge pump generating a voltage. The comparison signal is derived from an output signal of the PLL. The first charge pump modifies the first current according to the frequency difference and communicates the first current to the current summer. The second charge pump modifies the voltage according to the phase difference and communicates the voltage to the V2I converter.

Abstract: Generating an oscillating signal according to a control current includes receiving a control current corresponding to an oscillation frequency. A first differential signal and a second differential signal are generated by switching a first load according to the control current to yield the first differential signal, and switching a second load according to the control current to yield the second differential signal. The first load operates in opposition to the second load.

Abstract: An apparatus includes a voltage regulator operable to regulate a supply voltage to an on-chip module having an operational current, draw a supply current, and supply the operation current to the on-chip module. The supply current drawn by the voltage regulator is proportional to the operating current of the on-chip module.