Patents by Inventor Pratap Subrahmanyam
Pratap Subrahmanyam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11947458Abstract: A device is connected via a coherence interconnect to a CPU with a cache. The device monitors cache coherence events via the coherence interconnect, where the cache coherence events relate to the cache of the CPU. The device also includes a buffer that can contain representations, such as addresses, of cache lines. If a coherence event occurs on the coherence interconnect indicating that a cache line in the CPU's cache is dirty, then the device is configured to add an entry to the buffer to record the dirty cache line.Type: GrantFiled: July 27, 2018Date of Patent: April 2, 2024Assignee: VMware, Inc.Inventors: Irina Calciu, Jayneel Gandhi, Aasheesh Kolli, Pratap Subrahmanyam
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Patent number: 11914469Abstract: Disclosed are various embodiments for improving the resiliency and performance of clustered memory. A computing device can generate at least one parity page from at least a first local page and a second local page. The computing device can then submit a first write request for the first local page to a first one of a plurality of memory hosts. The computing device can also submit a second write request for the second local page to a second one of the plurality of memory hosts. Additionally, the computing device can submit a third write request for the parity page to a third one of the plurality of memory hosts.Type: GrantFiled: September 22, 2021Date of Patent: February 27, 2024Assignee: VMware, Inc.Inventors: Marcos K. Aguilera, Keerthi Kumar, Pramod Kumar, Pratap Subrahmanyam, Sairam Veeraswamy, Rajesh Venkatasubramanian
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Patent number: 11907065Abstract: Disclosed are various embodiments for improving the resiliency and performance of clustered memory. A computing device can generate at least one parity page from at least a first local page and a second local page. The computing device can then submit a first write request for the first local page to a first one of a plurality of memory hosts. The computing device can also submit a second write request for the second local page to a second one of the plurality of memory hosts. Additionally, the computing device can submit a third write request for the parity page to a third one of the plurality of memory hosts.Type: GrantFiled: January 25, 2023Date of Patent: February 20, 2024Assignee: VMware, Inc.Inventors: Marcos K. Aguilera, Keerthi Kumar, Pramod Kumar, Pratap Subrahmanyam, Sairam Veeraswamy, Rajesh Venkatasubramanian
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Publication number: 20240028243Abstract: In one set of embodiments, a hardware module of a computer system can receive a stream of addresses corresponding to memory units being accessed by a central processing unit (CPU) of the computer system. The hardware module can further generate a frequency estimate for each address in the stream of addresses, the frequency estimate being indicative of a number of times a memory unit identified by the address has been accessed by the CPU, and can determine, based on the generated frequency estimates, a set of n most frequently accessed memory units.Type: ApplicationFiled: July 21, 2022Publication date: January 25, 2024Inventors: Andreas Georg Nowatzyk, Isam Wadih Akkawi, Pratap Subrahmanyam, Adarsh Seethanadi Nayak, Nishchay Dua
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Patent number: 11880309Abstract: The state of cache lines transferred into an out of caches of processing hardware is tracked by monitoring hardware. The method of tracking includes monitoring the processing hardware for cache coherence events on a coherence interconnect between the processing hardware and monitoring hardware, determining that the state of a cache line has changed, and updating a hierarchical data structure to indicate the change in the state of said cache line. The hierarchical data structure includes a first level data structure including first bits, and a second level data structure including second bits, each of the first bits associated with a group of second bits. The step of updating includes setting one of the first bits and one of the second bits in the group corresponding to the first bit that is being set, according to an address of said cache line.Type: GrantFiled: June 23, 2021Date of Patent: January 23, 2024Assignee: VMware, Inc.Inventors: Nishchay Dua, Andreas Nowatzyk, Isam Wadih Akkawi, Pratap Subrahmanyam, Venkata Subhash Reddy Peddamallu, Adarsh Seethanadi Nayak
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Patent number: 11868644Abstract: In one set of embodiments, a hardware module of a computer system can receive a stream of addresses corresponding to memory units being accessed by a central processing unit (CPU) of the computer system. The hardware module can further generate a frequency estimate for each address in the stream of addresses, the frequency estimate being indicative of a number of times a memory unit identified by the address has been accessed by the CPU, and can determine, based on the generated frequency estimates, a set of n most frequently accessed memory units.Type: GrantFiled: July 21, 2022Date of Patent: January 9, 2024Assignee: VMWARE, INC.Inventors: Andreas Georg Nowatzyk, Isam Wadih Akkawi, Pratap Subrahmanyam, Adarsh Seethanadi Nayak, Nishchay Dua
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Patent number: 11782832Abstract: In a computer system, a processor and an I/O device controller communicate with each other via a coherence interconnect and according to a cache coherence protocol. Registers of the I/O device controllers are mapped to the cache coherent memory space to allow the processor to treat the registers as cacheable memory. As a result, latency of processor commands executed by the I/O device controller is decreased, and size of data stored in the I/O device controller that can be accessed by the processor is increased from the size of a single register to the size of an entire cache line.Type: GrantFiled: August 25, 2021Date of Patent: October 10, 2023Assignee: VMware, Inc.Inventors: Isam Wadih Akkawi, Andreas Nowatzyk, Pratap Subrahmanyam, Nishchay Dua, Adarsh Seethanadi Nayak, Venkata Subhash Reddy Peddamallu, Irina Calciu
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Publication number: 20230297257Abstract: Disclosed are various embodiments for improving resiliency and performance of clustered memory. A computing device can acquire a chunk of byte-addressable memory from a cluster memory host. The computing device can then identify an active set of allocated memory pages and an inactive set of allocated memory pages for a process executing on the computing device. Next, the computing device can store the active set of allocated memory pages for the process in the memory of the computing device. Finally, the computing device can store the inactive set of allocated memory pages for the process in the chunk of byte-addressable memory of the cluster memory host.Type: ApplicationFiled: May 24, 2023Publication date: September 21, 2023Inventors: Marcos K. AGUILERA, Keerthi KUMAR, Pramod KUMAR, Pratap SUBRAHMANYAM, Sairam VEERASWAMY, Rajesh VENKATASUBRAMANIAN
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Publication number: 20230273751Abstract: Disclosed are various embodiments for improving the resiliency and performance for clustered memory. A computing device can mark a page of the memory as being reclaimed. The computing device can then set the page of the memory as read-only. Next, the computing device can submit a write request for the contents of the page to individual ones of a plurality of memory hosts. Subsequently, the computing device can receive individual confirmations of a successful write of the page from the individual ones of the plurality of memory hosts. Then, the computing device can mark the page as free in response to receipt of the individual confirmations of the successful write from the individual ones of the plurality of memory hosts.Type: ApplicationFiled: May 5, 2023Publication date: August 31, 2023Inventors: MARCOS K. AGUILERA, KEERTHI KUMAR, PRAMOD KUMAR, PRATAP SUBRAHMANYAM, SAIRAM VEERASWAMY, RAJESH VENKATASUBRAMANIAN
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Patent number: 11740983Abstract: Techniques for implementing high availability for persistent memory are provided. In one embodiment, a first computer system can detect an alternating current (AC) power loss/cycle event and, in response to the event, can save data in a persistent memory of the first computer system to a memory or storage device that is remote from the first computer system and is accessible by a second computer system. The first computer system can then generate a signal for the second computer system subsequently to initiating or completing the save process, thereby allowing the second computer system to restore the saved data from the memory or storage device into its own persistent memory.Type: GrantFiled: September 28, 2021Date of Patent: August 29, 2023Assignee: VMware, Inc.Inventors: Pratap Subrahmanyam, Rajesh Venkatasubramanian, Kiran Tati, Qasim Ali
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Patent number: 11726811Abstract: Disclosed are various embodiments for decreasing the amount of time spent processing interrupts by switching contexts in parallel with processing an interrupt. An interrupt request can be received during execution of a process in a less privileged user mode. Then, the current state of the process can be saved. Next, a switch from the less privileged mode to a more privileged mode can be made. The interrupt request is then processed while in the more privileged mode. Subsequently or in parallel, and possibly prior to completion of the processing the interrupt request, another switch from the more privileged mode to the less privileged mode can be made.Type: GrantFiled: June 18, 2021Date of Patent: August 15, 2023Assignee: VMWARE, INC.Inventors: Yizhou Shan, Marcos Kawazoe Aguilera, Pratap Subrahmanyam, Rajesh Venkatasubramanian
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Patent number: 11720447Abstract: Techniques for achieving application high availability via application-transparent battery-backed replication of persistent data are provided. In one set of embodiments, a computer system can detect a failure that causes an application of the computer system to stop running. In response to detecting the failure, the computer system can copy persistent data written by the application and maintained locally at the computer system to one or more remote destinations, where the copying is performed in a manner that is transparent to the application and while the computer system runs on battery power. The application can then be restarted on another computer system using the copied data.Type: GrantFiled: January 7, 2021Date of Patent: August 8, 2023Assignee: VMware, Inc.Inventors: Pratap Subrahmanyam, Rajesh Venkatasubramanian, Kiran Tati, Qasim Ali, Marcos Aguilera, Irina Calciu, Venkata Subhash Reddy Peddamallu, Xavier Deguillard, Yi Yao
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Patent number: 11704030Abstract: Disclosed are various embodiments for improving resiliency and performance of clustered memory. A computing device can acquire a chunk of byte-addressable memory from a cluster memory host. The computing device can then identify an active set of allocated memory pages and an inactive set of allocated memory pages for a process executing on the computing device. Next, the computing device can store the active set of allocated memory pages for the process in the memory of the computing device. Finally, the computing device can store the inactive set of allocated memory pages for the process in the chunk of byte-addressable memory of the cluster memory host.Type: GrantFiled: September 22, 2021Date of Patent: July 18, 2023Assignee: VMWARE, INC.Inventors: Marcos K. Aguilera, Keerthi Kumar, Pramod Kumar, Pratap Subrahmanyam, Sairam Veeraswamy, Rajesh Venkatasubramanian
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Patent number: 11698760Abstract: Disclosed are various embodiments for improving the resiliency and performance of cluster memory. First, a computing device can submit a write request to a byte-addressable chunk of memory stored by a memory host, wherein the byte-addressable chunk of memory is read-only. Then, the computing device can determine that a page-fault occurred in response to the write request. Next, the computing device can copy a page associated with the write request from the byte-addressable chunk of memory to the memory of the computing device. Subsequently, the computing device can free the page from the memory host. Then, the computing device can update a page table entry for the page to refer to a location of the page in the memory of the computing device.Type: GrantFiled: September 22, 2021Date of Patent: July 11, 2023Assignee: VMWARE, INC.Inventors: Marcos K. Aguilera, Keerthi Kumar, Pramod Kumar, Pratap Subrahmanyam, Sairam Veeraswamy, Rajesh Venkatasubramanian
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Publication number: 20230205649Abstract: Techniques for implementing hardware-assisted memory disaggregation with recovery from network failures/problems are provided. In one set of embodiments, a hardware controller of a computer system can maintain a copy of a “remote memory” of the computer system (i.e., a section of the physical memory address space of the computer system that maps to a portion of the physical system memory of a remote computer system) in a local backup memory. The backup memory may be implemented using a non-volatile memory that is slower, but also less expensive, than conventional dynamic random-access memory (DRAM). Then, if the hardware controller is unable to retrieve data in the remote memory from the remote computer system within a specified time window due to, e.g., a network failure or other problem, the hardware controller can retrieve the data from the backup memory, thereby avoiding a hardware error condition (and potential application/system crash).Type: ApplicationFiled: February 27, 2023Publication date: June 29, 2023Inventors: Andreas Nowatzyk, Pratap Subrahmanyam, Isam Akkawi
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Patent number: 11687286Abstract: Disclosed are various embodiments for improving the resiliency and performance for clustered memory. A computing device can mark a page of the memory as being reclaimed. The computing device can then set the page of the memory as read-only. Next, the computing device can submit a write request for the contents of the page to individual ones of a plurality of memory hosts. Subsequently, the computing device can receive individual confirmations of a successful write of the page from the individual ones of the plurality of memory hosts. Then, the computing device can mark the page as free in response to receipt of the individual confirmations of the successful write from the individual ones of the plurality of memory hosts.Type: GrantFiled: September 22, 2021Date of Patent: June 27, 2023Assignee: VMWARE, INC.Inventors: Marcos K. Aguilera, Keerthi Kumar, Pramod Kumar, Pratap Subrahmanyam, Sairam Veeraswamy, Rajesh Venkatasubramanian
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Publication number: 20230168965Abstract: Disclosed are various embodiments for improving the resiliency and performance of clustered memory. A computing device can generate at least one parity page from at least a first local page and a second local page. The computing device can then submit a first write request for the first local page to a first one of a plurality of memory hosts. The computing device can also submit a second write request for the second local page to a second one of the plurality of memory hosts. Additionally, the computing device can submit a third write request for the parity page to a third one of the plurality of memory hosts.Type: ApplicationFiled: January 25, 2023Publication date: June 1, 2023Inventors: Marcos K. Aguilera, Keerthi Kumar, Pramod Kumar, Pratap Subrahmanyam, Sairam Veeraswamy, Rajesh Venkatasubramanian
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Patent number: 11650747Abstract: Disclosed are various embodiments for high throughput reclamation of pages in memory. A first plurality of pages in a memory of the computing device are identified to reclaim. In addition, a second plurality of pages in the memory of the computing device are identified to reclaim. The first plurality of pages are prepared for storage on a swap device of the computing device. Then, a write request is submitted to a swap device to store the first plurality of pages. After submission of the write request, the second plurality of pages are prepared for storage on the swap device while the swap device completes the write request.Type: GrantFiled: June 10, 2021Date of Patent: May 16, 2023Assignee: VMware, Inc.Inventors: Emmanuel Amaro Ramirez, Marcos Kawazoe Aguilera, Pratap Subrahmanyam, Rajesh Venkatasubramanian
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Patent number: 11620192Abstract: Techniques for implementing hardware-assisted memory disaggregation with recovery from network failures/problems are provided. In one set of embodiments, a hardware controller of a computer system can maintain a copy of a “remote memory” of the computer system (i.e., a section of the physical memory address space of the computer system that maps to a portion of the physical system memory of a remote computer system) in a local backup memory. The backup memory may be implemented using a non-volatile memory that is slower, but also less expensive, than conventional dynamic random-access memory (DRAM). Then, if the hardware controller is unable to retrieve data in the remote memory from the remote computer system within a specified time window due to, e.g., a network failure or other problem, the hardware controller can retrieve the data from the backup memory, thereby avoiding a hardware error condition (and potential application/system crash).Type: GrantFiled: July 10, 2020Date of Patent: April 4, 2023Assignee: VMware, Inc.Inventors: Andreas Nowatzyk, Pratap Subrahmanyam, Isam Akkawi
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Publication number: 20230069152Abstract: In a computer system, a processor and an I/O device controller communicate with each other via a coherence interconnect and according to a cache coherence protocol. Registers of the I/O device controllers are mapped to the cache coherent memory space to allow the processor to treat the registers as cacheable memory. As a result, latency of processor commands executed by the I/O device controller is decreased, and size of data stored in the I/O device controller that can be accessed by the processor is increased from the size of a single register to the size of an entire cache line.Type: ApplicationFiled: August 25, 2021Publication date: March 2, 2023Inventors: Isam Wadih AKKAWI, Andreas NOWATZYK, Pratap SUBRAHMANYAM, Nishchay DUA, Adarsh Seethanadi NAYAK, Venkata Subhash Reddy PEDDAMALLU, Irina CALCIU