Abstract: A method for developing a test sequence and for testing manufactured digital circuits. Test vectors are developed based on a simulation-based, directed-search approach. Specifically, from a given test vector, a next test vector is developed by altering the given test vector and determining the utility of the altered trial vector in propagating circuit faults to the primary outputs, based on a simulation of the circuit and a preselected cost function. The vector set is created through an iterative process of altering an accepted test vestor to develop a next trial vector. The vector set is efficiently developed by employing one phase that treats the entire set of circuit faults as the target, followed by another phase that targets specific faults that have not been detected in the previous phase.

Abstract: An arrangement for implementing graph operations, generally, and circuit simulations in particular employing a plurality of substantially identical high speed special purpose processing elements (PE) that are flexibly interconnected through a switch to form a cluster. In addition to the processing element (PE) being programmable, the interconnection switch permits dynamically altered routing of signals between the processing elements. The processing elements include a queue unit which permits high speed asynchronous communication between the elements. Additional advantage is attained with a hierarchical arrangement where a plurality of clusters are interconnected in an n-cube arrangement, and all of the clusters communicate with a host computer.

Abstract: A logic circuit simulator for detecting a spike condition at the output of a simulated gate. A plurality of autonomous devices are arranged for parallel pipeline operation. Each device is designed to perform only a part of the overall simulation function. One of the devices is responsive to signals representing gate input stimuli and to gate propagation delay data primarily for performing the spike analysis function. Another device performs the function of gate output signal scheduling in response to gate input stimuli for transmitting messages containing said signals to the spike analyzing device and other devices of the simulator. When the spike analyzing device detects a spike condition, it transmits into the pipeline signals indicating the scheduling of an unknown output event on the gate in question.