Patents by Inventor Praveen Nalla
Praveen Nalla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111524Abstract: An embodiment may involve persistent storage containing one or more tables, wherein the tables include entries that specify automations, wherein the automations are software applications. One or more processors are configured to: receive a specification for a new automation, wherein the specification includes a frequency at which the new automation is to be executed, and expected time or resources saved per execution; generate an automation request within the tables, wherein the automation request includes the frequency and the expected time or resources saved; generate a reference from the automation request to an automation configuration item (CI) in the tables, wherein the automation CI represents a software application used to perform the new automation; cause the software application to execute at least part of the new automation and in accordance with the frequency; and measure actual time or resources saved per execution of the new automation.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Inventors: Praveen Minnikaran Damodaran, Sameer Nalla, Rathijit Sarkar, Eric Schroeder, Binny Bhatnagar
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Patent number: 10262943Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.Type: GrantFiled: January 23, 2018Date of Patent: April 16, 2019Assignee: Lam Research CorporationInventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
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Patent number: 10103056Abstract: A method of depositing a metal seed for performing bottom-up gapfill of features of a substrate includes providing a substrate including a plurality of features; flowing a dilute metal precursor solution into the features, wherein the dilute metal precursor solution includes a metal precursor and a dilution liquid; evaporating the dilution liquid to locate the metal precursor at bottoms of the plurality of features; exposing the substrate to a plasma treatment to reduce the metal precursor to at least one of a metal or a metal alloy and to form a seed layer; performing a heat treatment on the substrate; and using a selective gapfill process to fill the features with a transition metal in contact with the seed layer.Type: GrantFiled: March 8, 2017Date of Patent: October 16, 2018Assignee: LAM RESEARCH CORPORATIONInventors: Samantha Tan, Boris Volosskiy, Taeseung Kim, Praveen Nalla, Novy Tjokro, Artur Kolics
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Publication number: 20180261502Abstract: A method of depositing a metal seed for performing bottom-up gapfill of features of a substrate includes providing a substrate including a plurality of features; flowing a dilute metal precursor solution into the features, wherein the dilute metal precursor solution includes a metal precursor and a dilution liquid; evaporating the dilution liquid to locate the metal precursor at bottoms of the plurality of features; exposing the substrate to a plasma treatment to reduce the metal precursor to at least one of a metal or a metal alloy and to form a seed layer; performing a heat treatment on the substrate; and using a selective gapfill process to fill the features with a transition metal in contact with the seed layer.Type: ApplicationFiled: March 8, 2017Publication date: September 13, 2018Inventors: Samantha Tan, Boris Volosskiy, Taeseung Kim, Praveen Nalla, Novy Tjokro, Artur KoIics
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Publication number: 20180151503Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.Type: ApplicationFiled: January 23, 2018Publication date: May 31, 2018Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
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Patent number: 9875968Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.Type: GrantFiled: February 24, 2017Date of Patent: January 23, 2018Assignee: Lam Research CorporationInventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
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Patent number: 9837312Abstract: Atomic layer etching (ALE) enables effective filling of small feature structures on semiconductor and other substrates, such as contacts and vias, by bottom-up fill, for example electroless deposition (ELD) of cobalt.Type: GrantFiled: October 5, 2016Date of Patent: December 5, 2017Assignee: LAM RESEARCH CORPORATIONInventors: Samantha Tan, Taeseung Kim, Jengyi Yu, Praveen Nalla, Novy Tjokro, Artur Kolics, Keren Jacobs Kanarik
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Patent number: 9818617Abstract: A solution for providing electroless deposition of a metal layer on a substrate is provided. A solvent is provided. A metal precursor is provided to the solvent. A first borane containing reducing agent is provided to the solvent. A second borane containing reducing agent is provided to the solvent, wherein the first borane containing reducing agent has a deposition rate of at least five times a deposition rate of the second borane containing reducing agent, and wherein the solution is free of nonborane reducing agents.Type: GrantFiled: December 8, 2016Date of Patent: November 14, 2017Assignee: Lam Research CorporationInventors: Artur Kolics, Praveen Nalla, Xiaomin Bin, Nanhai Li, Yaxin Wang, Patrick Little, Marina Polyanskaya
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Patent number: 9768063Abstract: A method for filling vias formed in a dielectric layer with a metal or metal alloy that has a low solubility with copper over copper containing interconnects, wherein the vias are part of a dual damascene structure with trenches and vias is provided. A sealing layer of a first metal or metal alloy that has a low solubility with copper is selectively deposited directly on the copper containing interconnects in at bottoms of the vias, wherein sidewalls of the dielectric layer forming the vias are exposed to the depositing the sealing layer, and wherein the first metal or metal alloy that has a low solubility is selectively deposited to only form a layer on the copper containing interconnects. A via fill of a second metal or metal alloy that has a low solubility with copper is electrolessly deposited over the sealing layer, which fills the vias.Type: GrantFiled: June 30, 2016Date of Patent: September 19, 2017Assignee: Lam Research CorporationInventors: Artur Kolics, Praveen Nalla, Lie Zhao
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Publication number: 20170162512Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.Type: ApplicationFiled: February 24, 2017Publication date: June 8, 2017Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
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Publication number: 20170092499Abstract: A solution for providing electroless deposition of a metal layer on a substrate is provided. A solvent is provided. A metal precursor is provided to the solvent. A first borane containing reducing agent is provided to the solvent. A second borane containing reducing agent is provided to the solvent, wherein the first borane containing reducing agent has a deposition rate of at least five times a deposition rate of the second borane containing reducing agent, and wherein the solution is free of nonborane reducing agents.Type: ApplicationFiled: December 8, 2016Publication date: March 30, 2017Inventors: Artur KOLICS, Praveen NALLA, Xiaomin BIN, Nanhai LI, Yaxin WANG, Patrick LITTLE, Marina POLYANSKAYA
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Patent number: 9583386Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.Type: GrantFiled: October 2, 2015Date of Patent: February 28, 2017Assignee: Lam Research CorporationInventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
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Patent number: 9551074Abstract: A solution for providing electroless deposition of a metal layer on a substrate is provided. A solvent is provided. A metal precursor is provided to the solvent. A first borane containing reducing agent is provided to the solvent. A second borane containing reducing agent is provided to the solvent, wherein the first borane containing reducing agent has a deposition rate of at least five times a deposition rate of the second borane containing reducing agent, and wherein the solution is free of nonborane reducing agents.Type: GrantFiled: June 5, 2014Date of Patent: January 24, 2017Assignee: Lam Research CorporationInventors: Artur Kolics, Praveen Nalla, Xiaomin Bin, Nanhai Li, Yaxin Wang, Patrick Little, Marina Polyanskaya
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Publication number: 20160273113Abstract: A method for providing an electroless plating over at least one copper containing layer is provided. Surfaces of the at least one copper containing layer are sealed by selectively depositing a sealing layer of catalytically active metal on the at least one copper containing layer. The sealing layer is exposed to an electroless deposition bath that is more reactive to the catalytically active metal than to the at least one copper containing layer to provide an electroless deposition on the sealing layer.Type: ApplicationFiled: May 26, 2016Publication date: September 22, 2016Inventors: Artur KOLICS, Praveen NALLA, Seshasayee VARADARAJAN
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Patent number: 9353444Abstract: A method for providing an electroless plating over at least one copper containing layer is provided. Surfaces of the at least one copper containing layer are sealed by selectively depositing a sealing layer of catalytically active metal on the at least one copper containing layer. The sealing layer is exposed to an electroless deposition bath that is more reactive to the catalytically active metal than to the at least one copper containing layer to provide an electroless deposition on the sealing layer.Type: GrantFiled: March 25, 2014Date of Patent: May 31, 2016Assignee: Lam Research CorporationInventors: Artur Kolics, Praveen Nalla, Seshasayee Varadarajan
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Publication number: 20160118296Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.Type: ApplicationFiled: October 2, 2015Publication date: April 28, 2016Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
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Patent number: 9287183Abstract: A method for detecting contamination on a patterned substrate includes: performing a via etch operation on a substrate, wherein the via etch operation is configured to define a via feature on the substrate and expose an etch-stop layer at a bottom of the via feature; performing an etch-stop removal operation on the substrate, wherein the etch-stop removal operation is configured for removing the etch-stop layer at the bottom of the via feature to expose a metallic feature underlying the etch-stop layer; applying an electroless deposition solution to the substrate, the applied electroless deposition solution configured for selectively depositing a metallic material over the exposed metallic feature and on metallic contaminants on exposed surfaces of the substrate, the metallic contaminants being generated from the metallic feature during the etch-stop removal operation; performing an inspection operation on the substrate to identify the metallic contaminants that have been deposited with the metallic material.Type: GrantFiled: March 31, 2015Date of Patent: March 15, 2016Assignee: Lam Research CorporationInventors: Larry Zhao, Artur Kolics, Praveen Nalla
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Publication number: 20150354064Abstract: A solution for providing electroless deposition of a metal layer on a substrate is provided. A solvent is provided. A metal precursor is provided to the solvent. A first borane containing reducing agent is provided to the solvent. A second borane containing reducing agent is provided to the solvent, wherein the first borane containing reducing agent has a deposition rate of at least five times a deposition rate of the second borane containing reducing agent, and wherein the solution is free of nonborane reducing agents.Type: ApplicationFiled: June 5, 2014Publication date: December 10, 2015Inventors: Artur KOLICS, Praveen NALLA, Xiaomin BIN, Nanhai LI, Yaxin WANG, Patrick LITTLE, Marina POLYANSKAYA
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Publication number: 20150275374Abstract: A method for providing an electroless plating over at least one copper containing layer is provided. Surfaces of the at least one copper containing layer are sealed by selectively depositing a sealing layer of catalytically active metal on the at least one copper containing layer. The sealing layer is exposed to an electroless deposition bath that is more reactive to the catalytically active metal than to the at least one copper containing layer to provide an electroless deposition on the sealing layer.Type: ApplicationFiled: March 25, 2014Publication date: October 1, 2015Inventors: Artur KOLICS, Praveen NALLA, Seshasayee VARADARAJAN
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Patent number: 7884017Abstract: Methods for cleaning semiconductor wafers following chemical mechanical polishing are provided. An exemplary method exposes a wafer to a thermal treatment in an oxidizing environment followed by a thermal treatment in a reducing environment. The thermal treatment in the oxidizing environment both removes residues and oxidizes exposed copper surfaces to form a cupric oxide layer. The thermal treatment in the reducing environment then reduces the cupric oxide to elemental copper. This leaves the exposed copper clean and in condition for further processing, such as electroless plating.Type: GrantFiled: February 3, 2010Date of Patent: February 8, 2011Assignee: Lam Research CorporationInventors: Zhonghui Alex Wang, Tiruchirapalli Arunagiri, Fritz C. Redeker, Yezdi Dordi, John Boyd, Mikhail Korolik, Arthur M. Howald, William Thie, Praveen Nalla