Patents by Inventor Praveen Prabha
Praveen Prabha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240146389Abstract: A computing device, includes one or more processors, configured to receive first data corresponding to a first radiofrequency signal received from a first wireless communication device, and second data corresponding to a second radiofrequency signal received from a second wireless communication device; select either the first wireless communication device or the second wireless communication device as a repeater device based on the first data or the second data according to one or more repeater selection criteria; instruct a transceiver to send a third radiofrequency signal to the repeater device, wherein the third radiofrequency signal comprises third data and an instruction for the repeater device to repeat the third data to the third wireless communication device.Type: ApplicationFiled: September 26, 2023Publication date: May 2, 2024Inventors: Sourav SAHA, Ingolf KARLS, Harish MITTY, Jayprakash THAKUR, Mythili HEGDE, Vijaya Prasad UMMELLA, Arun JAGADISH, Manjunath KAMATH, Praveen Kashyap Ananta BHAT, Padmesh MURUGAN LATHA, Satyajit Siddharay KAMAT, Manisha RAIGURU, Isha GARG, Abhijith PRABHA, Jay Vishnu GUPTA
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Patent number: 11876649Abstract: Equalization circuitry for a data channel in an integrated circuit device includes an analog equalization stage coupled to the data channel, and a digital signal processing stage downstream of the analog equalization stage. The digital signal processing stage generates control signals to control the analog equalization stage, and includes a digital equalization stage that operates on output of the analog equalization stage. The analog equalization stage may further include an enhanced processing stage for optical signals, which may be selectably coupled to the analog equalization stage. The analog equalization stage may include at least one feed-forward or feedback equalization stage, and a decision stage that outputs decision signals at one of a first plurality of signal levels. The enhanced processing stage operates on the decision signals to output enhanced decision signals at one of a second plurality of signal levels of higher resolution than the first plurality of signal levels.Type: GrantFiled: January 20, 2022Date of Patent: January 16, 2024Assignee: Marvell Asia Pte LtdInventors: Luke Wang, Benjamin Smith, Basel Alnabulsi, Stephane Dallaire, Simon Forey, Karthik Raviprakash, Praveen Prabha, Benjamin T. Reyes
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Patent number: 11855598Abstract: A variable gain amplifier includes input terminals configured to receive a differential input of the variable gain amplifier, output terminals configured to generate a differential output of the variable gain amplifier, the differential output having a gain applied by the variable gain amplifier to the differential input, and an impedance ladder circuit coupled to the input terminals, the impedance ladder circuit comprising a plurality of semiconductor switches configured to receive respective control signals based on a control voltage. The plurality of semiconductors switches are responsive to the respective control signals to adjust the gain of the variable gain amplifier and configured with a predetermined exponential scale such that the impedance ladder circuit causes a slope of the gain of the variable gain amplifier relative to the control voltage to be generally linear.Type: GrantFiled: August 25, 2022Date of Patent: December 26, 2023Assignee: Marvell Asia Pte Ltd.Inventors: Praveen Prabha, Karthik Raviprakash, Luke Wang, Stephane Dallaire
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Patent number: 11728817Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.Type: GrantFiled: January 3, 2022Date of Patent: August 15, 2023Assignee: MARVELL ASIA PTE LTDInventors: Mrunmay Talegaonkar, Jorge Pernillo, Junyi Sun, Praveen Prabha, Chang-Feng Loi, Yu Liao, Jamal Riani, Belal Helal, Karthik S. Gopalakrishnan, Aaron Buchwald
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Publication number: 20230037860Abstract: Equalization circuitry for a data channel in an integrated circuit device includes an analog equalization stage coupled to the data channel, and a digital signal processing stage downstream of the analog equalization stage. The digital signal processing stage generates control signals to control the analog equalization stage, and includes a digital equalization stage that operates on output of the analog equalization stage. The analog equalization stage may further include an enhanced processing stage for optical signals, which may be selectably coupled to the analog equalization stage. The analog equalization stage may include at least one feed-forward or feedback equalization stage, and a decision stage that outputs decision signals at one of a first plurality of signal levels. The enhanced processing stage operates on the decision signals to output enhanced decision signals at one of a second plurality of signal levels of higher resolution than the first plurality of signal levels.Type: ApplicationFiled: January 20, 2022Publication date: February 9, 2023Inventors: Luke Wang, Benjamin Smith, Basel Alnabulsi, Stephane Dallaire, Simon Forey, Karthik Raviprakash, Praveen Prabha, Benjamin T. Reyes
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Publication number: 20220407484Abstract: A variable gain amplifier includes input terminals configured to receive a differential input of the variable gain amplifier, output terminals configured to generate a differential output of the variable gain amplifier, the differential output having a gain applied by the variable gain amplifier to the differential input, and an impedance ladder circuit coupled to the input terminals, the impedance ladder circuit comprising a plurality of semiconductor switches configured to receive respective control signals based on a control voltage. The plurality of semiconductors switches are responsive to the respective control signals to adjust the gain of the variable gain amplifier and configured with a predetermined exponential scale such that the impedance ladder circuit causes a slope of the gain of the variable gain amplifier relative to the control voltage to be generally linear.Type: ApplicationFiled: August 25, 2022Publication date: December 22, 2022Inventors: Praveen PRABHA, Karthik Raviprakash, Luke Wang, Stephane Dallaire
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Patent number: 11463059Abstract: The present invention is directed to electrical circuits. In a specific embodiment, the present invention provides variable gain amplifier that includes an impedance ladder and a control circuit. The impedance ladder includes n switches configured in parallel. The control circuit includes a digital-to-analog converter and an amplifier. The control circuit generates n control signals for the n switches. There are other embodiments as well.Type: GrantFiled: March 23, 2021Date of Patent: October 4, 2022Assignee: Marvell Asia Pte Ltd.Inventors: Praveen Prabha, Karthik Raviprakash, Luke Wang, Stephane Dallaire
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Publication number: 20220311403Abstract: The present invention is directed to electrical circuits. In a specific embodiment, the present invention provides variable gain amplifier that includes an impedance ladder and a control circuit. The impedance ladder includes n switches configured in parallel. The control circuit includes a digital-to-analog converter and an amplifier. The control circuit generates n control signals for the n switches. There are other embodiments as well.Type: ApplicationFiled: March 23, 2021Publication date: September 29, 2022Inventors: Praveen PRABHA, Karthik RAVIPRAKASH, Luke WANG, Stephane DALLAIRE
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Publication number: 20220190836Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.Type: ApplicationFiled: January 3, 2022Publication date: June 16, 2022Inventors: Mrunmay TALEGAONKAR, Jorge PERNILLO, Junyi SUN, Praveen PRABHA, Chang-Feng LOI, Yu LIAO, Jamal RIANI, Belal HELAL, Karthik S. GOPALAKRISHNAN, Aaron BUCHWALD
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Patent number: 11218156Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.Type: GrantFiled: September 4, 2020Date of Patent: January 4, 2022Assignee: Marvell Asia Pte Ltd.Inventors: Mrunmay Talegaonkar, Jorge Pernillo, Junyi Sun, Praveen Prabha, Chang-Feng Loi, Yu Liao, Jamal Riani, Belal Helal, Karthik Gopalakrishnan, Aaron Buchwald
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Publication number: 20200403627Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.Type: ApplicationFiled: September 4, 2020Publication date: December 24, 2020Inventors: Mrunmay TALEGAONKAR, Jorge PERNILLO, Junyi SUN, Praveen PRABHA, Chang-Feng LOI, Yu LIAO, Jamal RIANI, Belal HELAL, Karthik Gopalakrishnan, Aaron BUCHWALD
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Patent number: 10804913Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.Type: GrantFiled: September 10, 2018Date of Patent: October 13, 2020Assignee: INPHI CORPORATIONInventors: Mrunmay Talegaonkar, Jorge Pernillo, Junyi Sun, Praveen Prabha, Chang-Feng Loi, Yu Liao, Jamal Riani, Belal Helal, Karthik Gopalakrishnan, Aaron Buchwald