Abstract: A plasma arc torch includes a cathode extending along an axis of the torch, a pilot arc conductor, and a nozzle body. A first fluid conduit and second fluid conduit extend parallel to the axis of the torch. A first offset fitting includes a first duct coupled to and in fluid communication with the first fluid conduit, and a second duct in fluid communication with the first duct and outwardly radially offset from the first duct and extending away from the first duct in a proximal direction. A second offset fitting includes a third duct coupled to and in fluid communication with the second fluid conduit, and a fourth duct in fluid communication with the third duct and outwardly radially offset from the third duct and extending away from the third duct in the proximal direction. A spring compression plug electrically connects the pilot arc conductor to the nozzle body.

Abstract: Systems and methods provide customers with a need-based warranty using a deep learning neural network. After categorizing, a customer need is mapped to a warranty type based on the SLA needs. Warranties may then be suggested based on customer need. In another embodiment, systems and methods detect an optimal warranty based on part failure and performance of a server. A mean time to resolve or replace can be minimized in future failure instances by comparing the derived replacement time with available warranty offerings to identify potential deviations and thereby recommend an optimal warranty from the available offerings. In a further embodiment, systems and methods identify and offer additional service contracts for vender services. A warranty proposer looks for warranty types that are emitted by a warranty-types analyzer and by a technical-support analyzer. The overlapping warranty offers are provided to customers.

Abstract: An example apparatus disclosed herein is to receive network data communicated via a first channel associated with the online collaboration session, the network data including received media data packets. The disclosed example apparatus is also to analyze the network data to determine first loopback data, the first loopback data including at least one of a first quality score based on a first analysis of the received media data packets or a second quality score based on a second analysis of media decoded from the received media data packets. The disclosed example apparatus is also to analyze local data obtained by a local client during the online collaboration session to determine second loopback data. The disclosed example apparatus is further to cause transmission of a loopback message to a moderator client via the second channel, the loopback message based on the first loopback data and the second loopback data.

Abstract: Systems, methods, and computer program products may store, in a distributed cache, a rule associated with a plurality of accounts in a Real-Time Payments (RTP) network, the rule being stored in association with account data associated with the plurality of accounts; receive an account level exclusion directive associated with the account; store, in the distributed cache, the account level exclusion directive in association with the account; receive transaction data associated with a transaction in the RTP network between the account and another account; retrieve, from the distributed cache, the rule, the account level exclusion directive, and the account data associated with the account; exclude, based on the account level exclusion directive, use of the rule for processing the transaction; and process, without applying the rule, the transaction in the RTP network.

Abstract: Built-in-self-test (BIST operations are performed by receiver lanes of a multilane receiver system, wherein at least one receiver lane is configured as a synthesized clock source for other receiver lanes configured to perform BIST operations. The at least one receiver lane configured as the synthesized clock source may generate a clock signal and provide the clock signal to the other receiver lanes performing the BIST operations. In some examples, digital control signals may be used for coordinating the enablement of the at least one receiver lane to function as the synthesized clock source and for coordinating the enablement of the other receiver lanes to perform BIST operations.

Abstract: Methods and systems for calibrating clock skew in a SerDes receiver. A method includes detecting a skew in a clock with respect to an edge of a reference clock, based on a value sampled by the clock and a value sampled by the reference clock at an edge of a data pattern, for a first Phase Interpolator (PI) code; determining a count of the skew from a de-serialized data word including outcome values obtained based on values sampled by the clock and values sampled by the reference clock at a predefined number of edges of the data pattern; obtaining a skew calibration code corresponding to the first PI code, from a binary variable obtained by accumulating an encoded variable to a previously generated binary variable; and calibrating the skew by performing a positive phase shift or a negative phase shift to the clock based on the skew calibration code.

Abstract: A method, a computer system, and a computer program product for detection of unintended dependencies between hardware design signals from pseudo-random number generator (PRNG) taps is provided. Embodiments of the present invention may include identifying one or more tap points in a design as an execution sequence. Embodiments of the present invention may include sampling the tap points by propagating the tap points in the design with different delays. Embodiments of the present invention may include defining observation points to identify tap collisions based on the tap points. Embodiments of the present invention may include identifying tap collisions. Embodiments of the present invention may include identifying one or more sources of the tap collisions in the design. Embodiments of the present invention may include eliminating the one or more sources of uninteresting tap collisions out of the tap collisions and filtering one or more of the tap collisions.

Abstract: The present disclosure provides systems and methods for performing built-in-self-test (BIST) operations without a dedicated clock source. The BIST operations are performed by receiver lanes of a multilane receiver system, wherein at least one receiver lane is configured as synthesized clock source for other receiver lanes configured to perform BIST operations. The at least one receiver lane configured as the synthesized clock source may generate a clock signal and provide the clock signal to the other receiver lanes performing the BIST operations. In some examples, digital control signals may be used for coordinating the enablement of the at least one receiver lane to function as the synthesized clock source and for coordinating the enablement of the other receiver lanes to perform BIST operations.

Abstract: Methods and systems for calibrating clock skew in a SerDes receiver. A method includes detecting a skew in a clock with respect to an edge of a reference clock, based on a value sampled by the clock and a value sampled by the reference clock at an edge of a data pattern, for a first Phase Interpolator (PI) code; determining a count of the skew from a de-serialized data word including outcome values obtained based on values sampled by the clock and values sampled by the reference clock at a predefined number of edges of the data pattern; obtaining a skew calibration code corresponding to the first PI code, from a binary variable obtained by accumulating an encoded variable to a previously generated binary variable; and calibrating the skew by performing a positive phase shift or a negative phase shift to the clock based on the skew calibration code.

Abstract: A symmetric multiprocessor includes with a hierarchical ring-based interconnection network is disclosed. The symmetric processor includes a plurality of buses comprised on the symmetric multiprocessor, wherein each of the buses are configured in a circular topology. The symmetric multiprocessor also includes a plurality of multi-processing nodes interconnected by the buses to make a hierarchical ring-based interconnection network for conveying commands between the multi-processing nodes. The interconnection network includes a command network configured to transport commands based on command tokens, wherein the tokens dictate a destination of the command, a partial response network configured to transport partial responses generated by the multi-processing nodes, and a combined response network configured to combine the partial responses generated by the multi-processing nodes using combined response tokens.

Abstract: A symmetric multiprocessor includes with a hierarchical ring-based interconnection network is disclosed. The symmetric processor includes a plurality of buses comprised on the symmetric multiprocessor, wherein each of the buses are configured in a circular topology. The symmetric multiprocessor also includes a plurality of multi-processing nodes interconnected by the buses to make a hierarchical ring-based interconnection network for conveying commands between the multi-processing nodes. The interconnection network includes a command network configured to transport commands based on command tokens, wherein the tokens dictate a destination of the command, a partial response network configured to transport partial responses generated by the multi-processing nodes, and a combined response network configured to combine the partial responses generated by the multi-processing nodes using combined response tokens.

Abstract: A symmetric multiprocessor includes with a hierarchical ring-based interconnection network is disclosed. The symmetric processor includes a plurality of buses comprised on the symmetric multiprocessor, wherein each of the buses are configured in a circular topology. The symmetric multiprocessor also includes a plurality of multi-processing nodes interconnected by the buses to make a hierarchical ring-based interconnection network for conveying commands between the multi-processing nodes. The interconnection network includes a command network configured to transport commands based on command tokens, wherein the tokens dictate a destination of the command, a partial response network configured to transport partial responses generated by the multi-processing nodes, and a combined response network configured to combine the partial responses generated by the multi-processing nodes using combined response tokens.

Abstract: The present disclosure describes a telemetry redundant measurement avoidance protocol (TRMAP) that solves redundant data collection problems in telemetry systems. The TRMAP can operate in a non-supervised environment and/or in a distributed manner, and does not require a central controller to manage multiple collection agents in one or multiple telemetry systems. The TRMAP can also be an opt-in-based protocol that favors altruistic data sharing and reuse between collection agents. In these ways, the TRMAP provides freedom and collaboration among developers or other entities that desired telemetry data, while allowing non-compliant collection agents to coexist, if possible.

Abstract: A method, a computer system, and a computer program product for detection of unintended dependencies between hardware design signals from pseudo-random number generator (PRNG) taps is provided. Embodiments of the present invention may include identifying one or more tap points in a design as an execution sequence. Embodiments of the present invention may include sampling the tap points by propagating the tap points in the design with different delays. Embodiments of the present invention may include defining observation points to identify tap collisions based on the tap points. Embodiments of the present invention may include identifying tap collisions. Embodiments of the present invention may include identifying one or more sources of the tap collisions in the design. Embodiments of the present invention may include eliminating the one or more sources of uninteresting tap collisions out of the tap collisions and filtering one or more of the tap collisions.

Abstract: An information handling system includes a basic input/output system (BIOS) that performs a firmware boot operation. During the firmware boot operation, the BIOS determines whether a driver pack management controller setting is enabled within a baseboard management controller of the information handling system. In response to the driver pack management controller setting being enabled, the BIOS copies a binary utility from the baseboard management controller to a system memory, and creates an operating system specific platform binary table to point to the binary utility on the baseboard management controller. In response to the operating system being initialized, a processor invokes the binary utility, mounts a memory partition of the baseboard management controller as a virtual drive of the operating system, and executes the operating system specific binary stage under a fixed globally unique identifier to install a driver pack.

Abstract: An information handling system includes a basic input/output system (BIOS) that performs a firmware boot operation. During the firmware boot operation, the BIOS determines whether a driver pack management controller setting is enabled within a baseboard management controller of the information handling system. In response to the driver pack management controller setting being enabled, the BIOS copies a binary utility from the baseboard management controller to a system memory, and creates an operating system specific platform binary table to point to the binary utility on the baseboard management controller. In response to the operating system being initialized, a processor invokes the binary utility, mounts a memory partition of the baseboard management controller as a virtual drive of the operating system, and executes the operating system specific binary stage under a fixed globally unique identifier to install a driver pack.

Abstract: According to one embodiment, a system includes a signaling connector comprising one or more wires. Each wire is capable of transmitting signaling between first and second components of an information handling system. A light-pipe is provided with the signaling connector. The light-pipe is capable of conveying light from one end of the signaling connector to another end of signaling connector so that the signaling connector can be traced.

Abstract: A technique for operating a data processing system includes determining, by an arbiter of a processing unit of the data processing system, whether an over-commit has occurred. In response to determining that the over-commit has occurred, the arbiter selects a broadcast command to be dropped based on a number of hops traversed through the data processing system by the broadcast command.

Abstract: Systems are provided for logging transactions in heterogeneous networks that include a combination of one or more instrumented components and one or more non-instrumented components. The instrumented components are configured to generate impersonated log records for the non-instrumented components involved in the transaction processing hand-offs with the instrumented components. The impersonated log records are persisted with other log records that are generated by the instrumented components in a transaction log that is maintained by a central logging system to reflect a complete flow of the transaction processing performed on the object, including the flow through the non-instrumented component(s).

Abstract: Systems are provided for logging transactions in heterogeneous networks that include a combination of one or more instrumented components and one or more non-instrumented components. The instrumented components are configured to generate impersonated log records for the non-instrumented components involved in the transaction processing hand-offs with the instrumented components. The impersonated log records are persisted with other log records that are generated by the instrumented components in a transaction log that is maintained by a central logging system to reflect a complete flow of the transaction processing performed on the object, including the flow through the non-instrumented component(s).