Abstract: An assembly for detecting a structural defect in a semiconductor die is provided. The assembly includes a defect-detection sensor and a microcontroller. The defect-detection sensor includes a plurality of resistive paths of electrical-conductive material in the semiconductor die, each of which has a first end and a second end and extends proximate a perimeter of the semiconductor die. The defect-detection sensor includes a plurality of signal-generation structures, each coupled to a respective resistive path and configured to supply a test signal to the resistive path. The microcontroller is configured to control the signal-generation structures to generate the test signals, acquire the test signals in each resistive paths, test an electrical feature of the resistive paths by performing an analysis of the test signals acquired and detect the presence of the structural defect in the semiconductor die based on a result of the analysis of the test signals acquired.

Abstract: A power transistor and a cascode transistor are connected in series. A driver circuit has an output driving a control terminal of the power transistor. The driver circuit has a first power supply node coupled to receive a floating voltage that is also applied to a control terminal of the cascode transistor. A variable voltage generator generates the floating voltage. The floating voltage track either a power supply voltage or a reference voltage over a first range of voltage levels for the power supply voltage. The floating voltage further satisfies a ratio metric relationship dependent on the power supply voltage and reference voltage over a second range of voltage levels for said power supply voltage.

Abstract: An on chip leakage-current detection device including a first inverter where the magnitude of delay of the output signal of the first inverter is determined by a leakage current of a target device. The leakage-current detection device further includes: a capacitor that is charged by the output signal of the first inverter; a second inverter coupled to capacitor that switches states when the capacitor is charged to a switching level; an odd number of additional inverters coupled in a sequence with a second-inverter output. The output of the leakage-current detection device has a frequency proportional to the leakage of the target device.

Abstract: A power transistor and a cascode transistor are connected in series. A driver circuit has an output driving a control terminal of the power transistor. The driver circuit has a first power supply node coupled to receive a floating voltage that is also applied to a control terminal of the cascode transistor. A variable voltage generator generates the floating voltage. The floating voltage track either a power supply voltage or a reference voltage over a first range of voltage levels for the power supply voltage. The floating voltage further satisfies a ratio metric relationship dependent on the power supply voltage and reference voltage over a second range of voltage levels for said power supply voltage.

Abstract: An on chip leakage-current detection device including a first inverter where the magnitude of delay of the output signal of the first inverter is determined by a leakage current of a target device. The leakage-current detection device further includes: a capacitor that is charged by the output signal of the first inverter; a second inverter coupled to capacitor that switches states when the capacitor is charged to a switching level; an odd number of additional inverters coupled in a sequence with a second-inverter output. The output of the leakage-current detection device has a frequency proportional to the leakage of the target device.

Abstract: An RC oscillator generates a periodic trigger signal, and a clock generator generates clock edges in response. A stuck-at-fault detection circuit detects a stuck-at-logic state of the periodic trigger signal and causes the RC oscillator to reset and causes a change in logic state of the periodic trigger signal. The RC oscillator includes first and second comparison circuits, a logic circuit receiving output from the first and second comparison circuits and generating the periodic trigger signal, and a clock generation circuit generating a clock signal therefrom. The stuck-at-fault detection circuit includes a capacitive node, charge circuitry charging the capacitive node based upon the periodic trigger signal, discharge circuitry discharging the capacitive node based upon the periodic trigger signal, and triggering circuitry asserting a reset signal to cause the RC oscillator to reset when the charge on the capacitive node indicates a stuck-at-logic state of the periodic trigger signal.

Abstract: A circuit includes an input terminal and a regulated supply line for supplying an electronic device with an electrostatic discharge protection and driver circuit for the electronic device. The supply line is coupled to the input terminal via the circuitry, so that current injected into the input terminal may produce a voltage increase on the regulated supply line. A comparator sensitive to the voltage at the input terminal and the voltage on the supply line is provided. A current sink coupled with the supply line and being activatable to sink current from the supply line is also provided. The comparator is configured for activating the current sink as a result of the voltage at the input terminal exceeding the voltage on the supply line of a certain intervention threshold.

Abstract: An RC oscillator generates a periodic trigger signal, and a clock generator generates clock edges in response. A stuck-at-fault detection circuit detects a stuck-at-logic state of the periodic trigger signal and causes the RC oscillator to reset and causes a change in logic state of the periodic trigger signal. The RC oscillator includes first and second comparison circuits, a logic circuit receiving output from the first and second comparison circuits and generating the periodic trigger signal, and a clock generation circuit generating a clock signal therefrom. The stuck-at-fault detection circuit includes a capacitive node, charge circuitry charging the capacitive node based upon the periodic trigger signal, discharge circuitry discharging the capacitive node based upon the periodic trigger signal, and triggering circuitry asserting a reset signal to cause the RC oscillator to reset when the charge on the capacitive node indicates a stuck-at-logic state of the periodic trigger signal.

Abstract: A circuit includes an input terminal and a regulated supply line for supplying an electronic device with an electrostatic discharge protection and driver circuit for the electronic device. The supply line is coupled to the input terminal via the circuitry, so that current injected into the input terminal may produce a voltage increase on the regulated supply line. A comparator sensitive to the voltage at the input terminal and the voltage on the supply line is provided. A current sink coupled with the supply line and being activatable to sink current from the supply line is also provided. The comparator is configured for activating the current sink as a result of the voltage at the input terminal exceeding the voltage on the supply line of a certain intervention threshold.

Abstract: A digital to analog converter (DAC) that reduces sub-threshold leakage current in PLLs includes three series connected transistors, a unity gain buffer, and a switch. The system is connected between the voltage-to-current converter and a current-controlled oscillator. The DAC receives and accurately mirrors a current signal generated by a voltage-to-current converter.

Abstract: A digital to analog converter (DAC) that reduces sub-threshold leakage current in PLLsincludes three series connected transistors, a unity gain buffer, and a switch. The system is connected between the voltage-to-current converter and a current-controlled oscillator. The DAC receives and accurately mirrors a current signal generated by a voltage-to-current converter.