Abstract: A DRAM controller which can be directly connected, without any automatic or selected reconfiguration, to DRAMs of various sizes. The externally-received address bits are remapped, so that the most significant two bits of the externally-received address bits are remapped onto the most significant bit of a row address and the most significant bit of a column address. This controller also provides selectable refresh periods.

Abstract: A DRAM controller which can be directly connected, without any automatic or selected reconfiguration, to DRAMs of various sizes. The externally-received address bits are remapped, so that the most significant two bits of the externally-received address bits are remapped onto the most significant bit of a row address and the most significant bit of a column address. This controller also provides selectable refresh periods.

Abstract: A memory circuit which has both RAM cells and ROM cells along a common row has a ROM cell which is directly connected to the word line for the row but which is not enabled when a logic state opposite to that represented by the ROM cell is attempted to be written into the ROM cell. Consequently the only word line required for enabling the ROM cells is the word line which enables the RAM cells.

Abstract: An electronic output buffer includes an inverter connected to an input line with several circuit devices for driving an output. The buffer further includes the programmable capability at manufacture for selecting one of several buffer configurations by selectively connecting the inverter and the input line to the circuit driving devices and by selectively connecting the circuit driving devices to one of at least two voltage sources.

Abstract: A digital processing system includes a memory for the storage of both data and instructions of M binary digit widths a N (N.noteq.M) binary digit parallel arithmetic and logic unit and self-test circuitry connected to the memory and connected to the arithmetic and logic unit for summing the numeric value of the contents of the memory into a set of sums that are N binary digit width and for comparing these sums with corresponding checksum constants to determine the integrity of the instructions stored in memory and the integrity of the arithmetic and logic unit operation.