Abstract: A built-in self test (BIST) may be performed on a device memory having two memory portions that are symmetrical (e.g., two symmetric halves of the device memory). The BIST may be run on the first memory portion. Error logic output from the first memory portion is captured (stored) in the second memory portion during the BIST run process. Error logic output from the first memory portion may include error data and an address of the memory error in the first memory portion. As the first and second memory portions are symmetric, the memory errors captured (stored) in the second memory portion are located at identical locations to the location of the memory errors in the first memory portion. A memory dump from the second memory portion after the BIST may provide a map of the memory errors in the first memory portion.

Abstract: Integrated circuits with multiport memory elements may be provided. A multiport memory element may include a latching circuit, a first set of address transistors, and a second set of address transistors. The latching circuit may include cross-coupled inverters, each of which includes a pull-up transistor and a pull-down transistor. The first set of address transistors may couple the latching circuit to a write port, whereas the second set of address transistors may couple the latching circuit to a read port. The pull-down transistors and the second set of address transistors may have body bias terminals that are controlled by a control signal. During data loading operations, the control signal may be temporarily elevated to weaken the pull-down transistors and the second set of address transistors to improve the write margin of the multiport memory element.

Abstract: A device includes an integrated circuit programmed with an operating surface equation. The operating surface equation may define an operating point as a function of operating voltage, operating frequency, leakage current, and one or more additional operating factors. The additional operating factors may be, for example, an operating temperature of the integrated circuit, a number of active execution units in the integrated circuit, and/or an age of the integrated circuit. The operating surface equation may be adjusted based on changes in one or more of the additional operating factors. Changes in the operating surface equation may change the operating surface of the integrated circuit. Thus, operating points (e.g., operating voltage) of the integrated circuit may be adjusted in response to changes in the additional operating factors.

Abstract: A binning process uses curve fitting to create and assign one or more bins based on testing data of operating voltage versus leakage current for test integrated circuits. Each bin is created by assigning an initial operating voltage to the bin and fitting a curve to the testing data population. An equation is generated describing the fitted curve. Integrated circuits are binned by measuring the leakage current at a selected operating voltage and testing the integrated circuit at one or more operating voltages determined based on the fitted curves. The integrated circuits are assigned a maximum operating voltage that corresponds to the lowest tested operating voltage at which the integrated circuit passes the test.

Abstract: A device includes an integrated circuit programmed with an operating surface equation. The operating surface equation may define an operating point as a function of operating voltage, operating frequency, and leakage current. The operating surface equation may be generated by fitting a surface equation to data for operating voltage and operating frequency versus leakage current for a plurality of test integrated circuits. An operating voltage of the integrated circuit at a given operating frequency may be determined by the operating surface equation and a leakage current value fused into the device.

Abstract: A device includes an integrated circuit programmed with an operating surface equation. The operating surface equation may define an operating point as a function of operating voltage, operating frequency, and leakage current. The operating surface equation may be generated by fitting a surface equation to data for operating voltage and operating frequency versus leakage current for a plurality of test integrated circuits. An operating voltage of the integrated circuit at a given operating frequency may be determined by the operating surface equation and a leakage current value fused into the device.

Abstract: A binning process uses curve fitting to create and assign one or more bins based on testing data of operating voltage versus leakage current for test integrated circuits. Each bin is created by assigning an initial operating voltage to the bin and fitting a curve to the testing data population. An equation is generated describing the fitted curve. Integrated circuits are binned by measuring the leakage current at a selected operating voltage and testing the integrated circuit at one or more operating voltages determined based on the fitted curves. The integrated circuits are assigned a maximum operating voltage that corresponds to the lowest tested operating voltage at which the integrated circuit passes the test.

Abstract: Integrated circuits with multiport memory elements may be provided. A multiport memory element may include a latching circuit, a first set of address transistors, and a second set of address transistors. The latching circuit may include cross-coupled inverters, each of which includes a pull-up transistor and a pull-down transistor. The first set of address transistors may couple the latching circuit to a write port, whereas the second set of address transistors may couple the latching circuit to a read port. The pull-down transistors and the second set of address transistors may have body bias terminals that are controlled by a control signal. During data loading operations, the control signal may be temporarily elevated to weaken the pull-down transistors and the second set of address transistors to improve the write margin of the multiport memory element.

Abstract: Adjustable positive voltage sag circuitry and adjustable ground bounce circuitry are provided for testing portions of integrated circuits. Adjustable positive voltage sag circuitry and adjustable ground bounce circuitry may provide positive power supply voltages with periodic sags and ground power supply voltages with periodic bounces to test a circuit under test. This may mimic a situation in which a circuit under test is surrounded by devices that switch simultaneously and consume power. Adjustable positive voltage sag circuitry and adjustable ground bounce circuitry allow for a circuit under test to be tested for robustness under such non-ideal power supply conditions.

Abstract: Integrated circuits with multiport memory elements may be provided. A multiport memory element may include a latching circuit, a first set of address transistors, and a second set of address transistors. The latching circuit may include cross-coupled inverters, each of which includes a pull-up transistor and a pull-down transistor. The first set of address transistors may couple the latching circuit to a write port, whereas the second set of address transistors may couple the latching circuit to a read port. The pull-down transistors and the second set of address transistors may have body bias terminals that are controlled by a control signal. During data loading operations, the control signal may be temporarily elevated to weaken the pull-down transistors and the second set of address transistors to improve the write margin of the multiport memory element.