Patents by Inventor Preston Pengra Briggs, III

Preston Pengra Briggs, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10884859
    Abstract: A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: January 5, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Laurence S. Kaplan, Preston Pengra Briggs, III, Miles Arthur Ohlrich, Willard Huston Leslie
  • Publication number: 20190243710
    Abstract: A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.
    Type: Application
    Filed: April 16, 2019
    Publication date: August 8, 2019
    Inventors: Laurence S. Kaplan, Preston Pengra Briggs, III, Miles Arthur Ohlrich, Willard Huston Leslie
  • Patent number: 10324792
    Abstract: A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: June 18, 2019
    Assignee: Cray Inc.
    Inventors: Laurence S. Kaplan, Preston Pengra Briggs, III, Miles Arthur Ohlrich, Willard Huston Leslie
  • Patent number: 10127109
    Abstract: A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: November 13, 2018
    Assignee: Cray, Inc.
    Inventors: Laurence S. Kaplan, Preston Pengra Briggs, III, Miles Arthur Ohlrich, Willard Huston Leslie
  • Patent number: 9910731
    Abstract: A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: March 6, 2018
    Assignee: Cray Inc.
    Inventors: Laurence S. Kaplan, Preston Pengra Briggs, III, Miles Arthur Ohlrich, Willard Huston Leslie
  • Publication number: 20170308430
    Abstract: A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.
    Type: Application
    Filed: June 16, 2017
    Publication date: October 26, 2017
    Inventors: Laurence S. Kaplan, Preston Pengra Briggs, III, Miles Arthur Ohlrich, Willard Huston Leslie
  • Publication number: 20170068596
    Abstract: A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.
    Type: Application
    Filed: November 21, 2016
    Publication date: March 9, 2017
    Inventors: Laurence S. Kaplan, Preston Pengra Briggs, III, Miles Arthur Ohlrich, Willard Huston Leslie
  • Patent number: 7739667
    Abstract: A system for conducting performance analysis for executing tasks. The analysis involves generating a variety of trace information related to performance measures, including parallelism-related information, during execution of the task. In order to generate the trace information, target source code of interest is compiled in such a manner that executing the resulting executable code will generate execution trace information composed of a series of events. Each event stores trace information related to a variety of performance measures for the one or more processors and protection domains used. After the execution trace information has been generated, the system can use that trace information and a trace information description file to produce useful performance measure information. The trace information description file contains information that describes the types of execution events as well as the structure of the stored information.
    Type: Grant
    Filed: October 19, 2005
    Date of Patent: June 15, 2010
    Assignee: Cray Inc.
    Inventors: Charles David Callahan, II, Keith Arnett Shields, Preston Pengra Briggs, III
  • Patent number: 6961925
    Abstract: A system for conducting performance analysis for executing tasks. The analysis involves generating a variety of trace information related to performance measures, including parallelism-related information, during execution of the task. In order to generate the trace information, target source code of interest is compiled in such a manner that executing the resulting executable code will generate execution trace information composed of a series of events. Each event stores trace information related to a variety of performance measures for the one or more processors and protection domains used. After the execution trace information has been generated, the system can use that trace information and a trace information description file to produce useful performance measure information. The trace information description file contains information that describes the types of execution events as well as the structure of the stored information.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: November 1, 2005
    Assignee: Cray Inc.
    Inventors: Charles David Callahan, II, Keith Arnett Shields, Preston Pengra Briggs, III
  • Patent number: 6230313
    Abstract: A system for conducting performance analysis for executing tasks. The analysis involves generating a variety of trace information related to performance measures, including parallelism-related information, during execution of the task. In order to generate the trace information, target source code of interest is compiled in such a manner that executing the resulting executable code will generate execution trace information composed of a series of events. Each event stores trace information related to a variety of performance measures for the one or more processors and protection domains used. After the execution trace information has been generated, the system can use that trace information and a trace information description file to produce useful performance measure information. The trace information description file contains information that describes the types of execution events as well as the structure of the stored information.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: May 8, 2001
    Assignee: Cray Inc.
    Inventors: Charles David Callahan, II, Keith Arnett Shields, Preston Pengra Briggs, III