Abstract: A central arbiter uses priority generators to determine which resource on a shared bus has priority in accessing the bus. Each resource has a corresponding priority generator. Each priority generator has a counter having inputs and outputs. A starting value is provided at the inputs and the priority value is obtained from the outputs. Each priority generator has a comparator that compares the outputs of a counter with a modulo number of the counters, N. The priority generators provide a combination of fixed priority and round robin arbitration schemes. By selecting the value of N relative to the number of resources, the rate of round robin access relative to fixed priority access can be set.

Abstract: A uniprocessor if formed on plural independently controlled chips each including a primary instruction driven controller and a secondary error driven self-sequencing controller. Each instruction is supplied in parallel to each primary controller which generates an EXIT signal, as it completes execution, to a common external EXIT line. Hardware monitors the local EXIT signal and the common EXIT line state and activates the secondary controller, when a mismatch is detected, to set an on-chip reset predominant error latch driving a common external ERROR line, an ERROR-state on which also sets the latches and activates any inactive secondary controller to drive its chip to a first predetermined state and to reset its latch. When no ERROR signal remains, the secondary controllers cycle in synchronism through an ERROR routine, exiting to instruction control.