Patents by Inventor Primit Modi

Primit Modi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10424358
    Abstract: Disclosed is a device including a selected distributed driver, a first feedback control circuit, and a second feedback control circuit. The first feedback control circuit is coupled to the selected distributed driver. The first feedback control circuit is configured to maintain an output of the selected distributed driver within a first predetermined range. The second feedback control circuit is selectively coupled to the selected distributed driver and is configured to maintain the output of the selected distributed driver to be within a second predetermined range. The second predetermined range is within the first predetermined range.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: September 24, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Supraja Sundaresan, Sung-en Wang, Khin Htoo, Primit Modi
  • Patent number: 10284182
    Abstract: A complementary signal path may include an amplifier circuit configured to receive a pair of complementary input signals and a data alignment circuit configured to output a pair of complementary output signals in response to the pair of complementary input signals. A control circuit may detect duty cycle distortion in the pair of complementary output signals and perform a duty cycle correction process to remove the distortion. To do so, the control circuit may search for target current amounts in response to the duty cycle distortion and inject a control current into the amplifier circuit at the target current amounts.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: May 7, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Primit Modi, Venkatesh Ramachandra, Tianyu Tang, Srinivas Rajendra
  • Publication number: 20180358069
    Abstract: Disclosed is a device including a selected distributed driver, a first feedback control circuit, and a second feedback control circuit. The first feedback control circuit is coupled to the selected distributed driver. The first feedback control circuit is configured to maintain an output of the selected distributed driver within a first predetermined range. The second feedback control circuit is selectively coupled to the selected distributed driver and is configured to maintain the output of the selected distributed driver to be within a second predetermined range. The second predetermined range is within the first predetermined range.
    Type: Application
    Filed: January 12, 2018
    Publication date: December 13, 2018
    Inventors: Supraja SUNDARESAN, Sung-en WANG, Khin HTOO, Primit MODI
  • Publication number: 20180175834
    Abstract: A complementary signal path may include an amplifier circuit configured to receive a pair of complementary input signals and a data alignment circuit configured to output a pair of complementary output signals in response to the pair of complementary input signals. A control circuit may detect duty cycle distortion in the pair of complementary output signals and perform a duty cycle correction process to remove the distortion. To do so, the control circuit may search for target current amounts in response to the duty cycle distortion and inject a control current into the amplifier circuit at the target current amounts.
    Type: Application
    Filed: June 30, 2017
    Publication date: June 21, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Primit Modi, Venkatesh Ramachandra, Tianyu Tang, Srinivas Rajendra
  • Patent number: 9792994
    Abstract: A driver circuit, such as could be used as an off-chip driver for an I/O pin on a memory circuit, is presented. The driver has a PMOS connected between a supply level and the driver's output node. In an active mode, the bulk terminal of the PMOS is connected to the supply level; and in a standby mode, the PMOS's bulk terminal is set to a higher level. This reduces the leakage current through the PMOS in the standby mode, allowing for smaller device with a lower capacitance to be used.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: October 17, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Primit Modi, Venkatesh Ramachandra