Abstract: Trace transfer techniques can be used to couple touch electrodes to touch sensing circuitry with a reduced border region around a touch sensor panel. Touch electrodes on a first side of the substrate can be routed to a bond pad region on the second side of the substrate via a trace transfer technique to enable single-sided bonding of a double-sided touch sensor panel. Trace transfer techniques can also be used to couple conductive traces on a first side of the substrate to a flex circuit oriented perpendicular to or otherwise not parallel to the first side of the substrate. Orienting the flex circuit in this way can allow the flex circuit to connect to touch circuitry with reduced bending as compared with the amount of bending of the flex circuit when oriented substantially parallel to the substrate.

Abstract: Trace transfer techniques can be used to couple touch electrodes to touch sensing circuitry with a reduced border region around a touch sensor panel. Touch electrodes on a first side of the substrate can be routed to a bond pad region on the second side of the substrate via a trace transfer technique to enable single-sided bonding of a double-sided touch sensor panel. Trace transfer techniques can also be used to couple conductive traces on a first side of the substrate to a flex circuit oriented perpendicular to or otherwise not parallel to the first side of the substrate. Orienting the flex circuit in this way can allow the flex circuit to connect to touch circuitry with reduced bending as compared with the amount of bending of the flex circuit when oriented substantially parallel to the substrate.

Abstract: The disclosure relates to a touch screen including a first electrode layer, a second electrode layer, and a third electrode layer. The touch screen can include shield-sensor vias connecting the first electrode layer and the second electrode layer and shield-shield vias connecting the first electrode layer and the third electrode layer, for example. The shield-sensor vias can be placed in a bond pad region of the touch screen, which can further include connections between one or more routing traces connected to one or more touch electrodes and touch or other circuitry further included in the electronic device. The shield-shield vias can be placed in an outer region located around an inner region of the touch screen. In some examples, one or more routing traces can include diverted portions to maintain a threshold distance between the routing traces and the one or more shield-shield vias.

Abstract: A hybrid laser modulation and acid etch process for the creation of a patterned substrate. According to some embodiments, a hole is formed in a glass substrate by first modulating a portion of the substrate in the desired shape. A mask is coated on the glass substrate and is patterned to expose the modulated portion. The glass substrate is then acid etched to remove the modulated portion. Once the modulated portion has been etched, the desired shape may be removed from the glass substrate and the mask may be stripped.

Abstract: The disclosure relates to a touch screen including a first electrode layer, a second electrode layer, and a third electrode layer. The touch screen can include shield-sensor vias connecting the first electrode layer and the second electrode layer and shield-shield vias connecting the first electrode layer and the third electrode layer, for example. The shield-sensor vias can be placed in a bond pad region of the touch screen, which can further include connections between one or more routing traces connected to one or more touch electrodes and touch or other circuitry further included in the electronic device. The shield-shield vias can be placed in an outer region located around an inner region of the touch screen. In some examples, one or more routing traces can include diverted portions to maintain a threshold distance between the routing traces and the one or more shield-shield vias.

Abstract: Methods and techniques for fabricating metal interconnects, lines, or vias by subtractive etching and liner deposition methods are provided. Methods involve depositing a blanket copper layer, removing regions of the blanket copper layer to form a pattern, treating the patterned metal, depositing a copper-dielectric interface material such that the copper-dielectric interface material adheres only to the patterned copper, depositing a dielectric barrier layer on the substrate, and depositing a dielectric bulk layer on the substrate.

Abstract: Methods and techniques for fabricating metal interconnects, lines, or vias by subtractive etching and liner deposition methods are provided. Methods involve depositing a blanket copper layer, removing regions of the blanket copper layer to form a pattern, treating the patterned metal, depositing a copper-dielectric interface material such that the copper-dielectric interface material adheres only to the patterned copper, depositing a dielectric barrier layer on the substrate, and depositing a dielectric bulk layer on the substrate.

Abstract: A hybrid laser modulation and acid etch process for the creation of a patterned substrate. According to some embodiments, a hole is formed in a glass substrate by first modulating a portion of the substrate in the desired shape. A mask is coated on the glass substrate and is patterned to expose the modulated portion. The glass substrate is then acid etched to remove the modulated portion. Once the modulated portion has been etched, the desired shape may be removed from the glass substrate and the mask may be stripped.

Abstract: Methods and techniques for fabricating metal interconnects, lines, or vias by subtractive etching and liner deposition methods are provided. Methods involve depositing a blanket copper layer, removing regions of the blanket copper layer to form a pattern, treating the patterned metal, depositing a copper-dielectric interface material such that the copper-dielectric interface material adheres only to the patterned copper, depositing a dielectric barrier layer on the substrate, and depositing a dielectric bulk layer on the substrate.

Abstract: An electronic device may have layers of glass for forming components such as a display. A display cover glass layer may overlap an array of pixels. A touch sensor may be formed under the display cover glass layer. Conductive structures such as transparent conductive electrodes or other conductive layers of material may be formed on the outer surface of the display cover glass layer. The electrodes on the outer surface of the display cover glass layer may be coupled to metal contacts and other circuitry on the inner surface of the display cover glass layer using conductive vias. Vias may be provided with barrier layers, opaque coatings, tapers, and other structures and may be formed using techniques that enhance compatibility with chemical strengthening processes.

Abstract: A method of opening a barrier film below copper structures in a stack is provided. A pulsed gas is provided into a plasma processing chamber, wherein the providing the pulsed gas comprises providing a pulsed H2 containing gas and providing a pulsed halogen containing gas, wherein the pulsed H2 containing gas and the pulsed halogen containing gas are pulsed out of phase, and wherein the pulsed H2 containing gas has an H2 high flow period and the pulsed halogen containing gas has a halogen containing gas high flow period, wherein the H2 high flow period is greater than the halogen containing gas high flow period. The pulsed gas is formed into a plasma. The copper structures and the barrier film are exposed to the plasma, which etches the barrier film. In another embodiment, a wet and dry cyclical process may be used.

Abstract: Initiation conditions and strain techniques are described that enable forming high quality GaAsP semiconductor material on an SiGe semiconductor material with low threading defect density. Suitable initiation conditions include exposing the SiGe semiconductor material to a gas comprising arsenic. A tensilely-strained region may be formed in the semiconductor structure between regions of GaAsP semiconductor material and SiGe semiconductor material.

Abstract: A method for etching a stack with at least one metal layer in one or more cycles is provided. An initiation step is preformed, transforming part of the at least one metal layer into metal oxide, metal halide, or lattice damaged metallic sites. A reactive step is performed providing one or more cycles, where each cycle comprises providing an organic solvent vapor to form a solvated metal, metal halide, or metal oxide state and providing an organic ligand solvent to form volatile organometallic compounds.

Abstract: A method of opening a barrier film below copper structures in a stack is provided. A pulsed gas is provided into a plasma processing chamber, wherein the providing the pulsed gas comprises providing a pulsed H2 containing gas and providing a pulsed halogen containing gas, wherein the pulsed H2 containing gas and the pulsed halogen containing gas are pulsed out of phase, and wherein the pulsed H2 containing gas has an H2 high flow period and the pulsed halogen containing gas has a halogen containing gas high flow period, wherein the H2 high flow period is greater than the halogen containing gas high flow period. The pulsed gas is formed into a plasma. The copper structures and the barrier film are exposed to the plasma, which etches the barrier film. In another embodiment, a wet and dry cyclical process may be used.

Abstract: Methods and techniques for fabricating metal interconnects, lines, or vias by subtractive etching and liner deposition methods are provided. Methods involve depositing a blanket copper layer, removing regions of the blanket copper layer to form a pattern, treating the patterned metal, depositing a copper-dielectric interface material such that the copper-dielectric interface material adheres only to the patterned copper, depositing a dielectric barrier layer on the substrate, and depositing a dielectric bulk layer on the substrate.

Abstract: A method for etching a stack with at least one metal layer in one or more cycles is provided. An initiation step is preformed, transforming part of the at least one metal layer into metal oxide, metal halide, or lattice damaged metallic sites. A reactive step is performed providing one or more cycles, where each cycle comprises providing an organic solvent vapor to form a solvated metal, metal halide, or metal oxide state and providing an organic ligand solvent to form volatile organometallic compounds.

Abstract: A method for etching a stack with at least one metal layer in one or more cycles is provided. An initiation step is preformed, transforming part of the at least one metal layer into metal oxide, metal halide, or lattice damaged metallic sites. A reactive step is performed providing one or more cycles, where each cycle comprises providing an organic solvent vapor to form a solvated metal, metal halide, or metal oxide state and providing an organic ligand solvent to form volatile organometallic compounds. A desorption of the volatile organometallic compounds is performed.

Abstract: Initiation conditions and strain techniques are described that enable forming high quality GaAsP semiconductor material on an SiGe semiconductor material with low threading defect density. Suitable initiation conditions include exposing the SiGe semiconductor material to a gas comprising arsenic. A tensilely-strained region may be formed in the semiconductor structure between regions of GaAsP semiconductor material and SiGe semiconductor material.

Abstract: A method for etching a stack with at least one metal layer in one or more cycles is provided. An initiation step is preformed, transforming part of the at least one metal layer into metal oxide, metal halide, or lattice damaged metallic sites. A reactive step is performed providing one or more cycles, where each cycle comprises providing an organic solvent vapor to form a solvated metal, metal halide, or metal oxide state and providing an organic ligand solvent to form volatile organometallic compounds. A desorption of the volatile organometallic compounds is performed.