Patents by Inventor Priya Walimbe

Priya Walimbe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210098987
    Abstract: Some embodiments include apparatuses and methods using a conductive connection, a first die, and a second die arranged in a stack with the first die. The first die includes a first electrode static discharge (ESD) protection structure, which includes a first number circuit elements coupled to the conductive connection. The second die includes a second ESD protection structure, which includes a second number of circuit elements coupled to the first number of circuit elements. The first number of circuit elements and the second number of circuit elements are based on a combined model of the first and second ESD protection structures.
    Type: Application
    Filed: September 26, 2019
    Publication date: April 1, 2021
    Inventors: Priya Walimbe, Steven S. Poon, Marco Escalante, Abhishek Sharma
  • Patent number: 7319616
    Abstract: In one embodiment, the present invention includes a method to supply a negative voltage to at least one deselected wordline of a memory array. Further, while the negative voltage is supplied to deselected wordlines, a positive voltage may be supplied to a selected wordline. The memory array may be a flash memory incorporating multi-level cell architecture, in one embodiment.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: January 15, 2008
    Assignee: Intel Corporation
    Inventors: Rajesh Sundaram, Jahanshir Javanifard, Kerry D. Tedrow, Priya Walimbe, Tom H. Ly, Raymond W. Zeng
  • Publication number: 20050105338
    Abstract: In one embodiment, the present invention includes a method to supply a negative voltage to at least one deselected wordline of a memory array. Further, while the negative voltage is supplied to deselected wordlines, a positive voltage may be supplied to a selected wordline. The memory array may be a flash memory incorporating multi-level cell architecture, in one embodiment.
    Type: Application
    Filed: November 13, 2003
    Publication date: May 19, 2005
    Inventors: Rajesh Sundaram, Jahanshir Javanifard, Kerry Tedrow, Priya Walimbe, Tom Ly, Raymond Zeng
  • Patent number: 6744669
    Abstract: A DC voltage boost circuit capable of improved efficiency. The DC voltage boost circuit includes an inductive element, a switching device, an output capacitive element, and a regulation circuit. The switching device periodically causes current to flow through the inductive element in response to a control signal. Each time the switching device causes current to flow through the inductive element, the inductive element stores the energy. When the switching device stops the current from flowing through the inductive element, the stored energy is then transferred to the output capacitive element. The capacitive element accumulates the packets of energy stored in the inductive element in the form of charges to form the output voltage of the booster. A regulation circuit is provided to sample the booster output voltage and to generate the control signal for the switching device such that the output voltage is regulated. The control signal can be frequency modulated or pulse width modulated.
    Type: Grant
    Filed: June 17, 2002
    Date of Patent: June 1, 2004
    Assignee: Intel Corporation
    Inventors: Javanifard Jahanshir, Priya Walimbe, Richard B. Foehringer
  • Patent number: 6734655
    Abstract: A DC voltage boost circuit including a regulation circuit that produces a pulse width modulated control signal for regulating the output of the DC voltage boost circuit. Various embodiments of regulation circuits are disclosed. In one embodiment, the regulation circuit includes a waveform generator for generating a triangular waveform and a comparator for producing the pulse width modulated control signal by comparing the triangular waveform with a voltage that varies proportional to the booster output voltage. In another embodiment, the regulation circuit includes a waveform generator for generating a sawtooth waveform whose rise time varies inversely with the booster output voltage and a comparator for producing the pulse width modulated control signal by comparing the modulated sawtooth waveform with a substantially constant voltage.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: May 11, 2004
    Assignee: Intel Corporation
    Inventors: Jahanshir Javanifard, Priya Walimbe
  • Patent number: 6552600
    Abstract: An improvement in initializing a charge pump circuit. After a charge pump circuit is turned off, the relatively high voltages in its nodes are discharged (initialized) to prevent electrical stress and eventual component failure. The transistors used to discharge these nodes receive a control signal of the same polarity as the voltage being discharged. When the charge pump is generating a negative voltage, the output of the final stage of the pump can be used to provide this negative control signal to discharge the negative voltages from the internal nodes. A delayed second signal can be used to discharge the final stage.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: April 22, 2003
    Assignee: Intel Corporation
    Inventors: Priya Walimbe, Rajesh Sundaram, Bo Li
  • Publication number: 20030006742
    Abstract: A DC voltage boost circuit capable of improved efficiency. The DC voltage boost circuit includes an inductive element, a switching device, an output capacitive element, and a regulation circuit. The switching device periodically causes current to flow through the inductive element in response to a control signal. Each time the switching device causes current to flow through the inductive element, the inductive element stores the energy. When the switching device stops the current from flowing through the inductive element, the stored energy is then transferred to the output capacitive element. The capacitive element accumulates the packets of energy stored in the inductive element in the form of charges to form the output voltage of the booster. A regulation circuit is provided to sample the booster output voltage and to generate the control signal for the switching device such that the output voltage is regulated. The control signal can be frequency modulated or pulse width modulated.
    Type: Application
    Filed: June 17, 2002
    Publication date: January 9, 2003
    Inventors: Javanifard Jahanshir, Priya Walimbe, Richard B. Foehringer
  • Patent number: 6469482
    Abstract: A DC voltage boost circuit capable of improved efficiency. The DC voltage boost circuit includes an inductive element, a switching device, an output capacitive element, and a regulation circuit. The switching device periodically causes current to flow through the inductive element in response to a control signal. Each time the switching device causes current to flow through the inductive element, the inductive element stores the energy. When the switching device stops the current from flowing through the inductive element, the stored energy is then transferred to the output capacitive element. The capacitive element accumulates the packets of energy stored in the inductive element in the form of charges to form the output voltage of the booster. A regulation circuit is provided to sample the booster output voltage and to generate the control signal for the switching device such that the output voltage is regulated. The control signal can be frequency modulated or pulse width modulated.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: October 22, 2002
    Assignee: Intel Corporation
    Inventors: Javanifard Jahanshir, Priya Walimbe, Richard B. Foehringer
  • Publication number: 20020130700
    Abstract: An improvement in initializing a charge pump circuit. After a charge pump circuit is turned off, the relatively high voltages in its nodes are discharged (initialized) to prevent electrical stress and eventual component failure. The transistors used to discharge these nodes receive a control signal of the same polarity as the voltage being discharged. When the charge pump is generating a negative voltage, the output of the final stage of the pump can be used to provide this negative control signal to discharge the negative voltages from the internal nodes. A delayed second signal can be used to discharge the final stage.
    Type: Application
    Filed: March 15, 2001
    Publication date: September 19, 2002
    Inventors: Priya Walimbe, Rajesh Sundaram, Bo Li