Patents by Inventor PRIYAMBADA MITRA

PRIYAMBADA MITRA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10467139
    Abstract: A cache coherence system manages both internode and intranode cache coherence in a cluster of nodes. Each node in the cluster of nodes is either a collection of processors running an intranode coherence protocol between themselves, or a single processor. A node comprises a plurality of coherence ordering units (COUs) that are hardware circuits configured to manage intranode coherence of caches within the node and/or internode coherence with caches on other nodes in the cluster. Each node contains one or more directories which tracks the state of cache line entries managed by the particular node. Each node may also contain one or more scoreboards for managing the status of ongoing transactions. The internode cache coherence protocol implemented in the COUs may be used to detect and resolve communications errors, such as dropped message packets between nodes, late message delivery at a node, or node failure.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: November 5, 2019
    Assignee: Oracle International Corporation
    Inventors: Paul N. Loewenstein, Damien Walker, Priyambada Mitra, Ali Vahidsafa, Matthew Cohen, Josephus Ebergen, Andrew Brock
  • Patent number: 10452547
    Abstract: A cache coherence system manages both internode and intranode cache coherence in a cluster of nodes. Each node in the cluster of nodes is either a collection of processors running an intranode coherence protocol between themselves, or a single processor. A node comprises a plurality of coherence ordering units (COUs) that are hardware circuits configured to manage intranode coherence of caches within the node and/or internode coherence with caches on other nodes in the cluster. Each node contains one or more directories which tracks the state of cache line entries managed by the particular node. Each node may also contain one or more scoreboards for managing the status of ongoing transactions. The internode cache coherence protocol implemented in the COUs may be used to detect and resolve communications errors, such as dropped message packets between nodes, late message delivery at a node, or node failure.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: October 22, 2019
    Assignee: Oracle International Corporation
    Inventors: Paul N. Loewenstein, Damien Walker, Priyambada Mitra, Ali Vahidsafa, Matthew Cohen, Josephus Ebergen, Andrew Brock
  • Publication number: 20190205252
    Abstract: A cache coherence system manages both internode and intranode cache coherence in a cluster of nodes. Each node in the cluster of nodes is either a collection of processors running an intranode coherence protocol between themselves, or a single processor. A node comprises a plurality of coherence ordering units (COUs) that are hardware circuits configured to manage intranode coherence of caches within the node and/or internode coherence with caches on other nodes in the cluster. Each node contains one or more directories which tracks the state of cache line entries managed by the particular node. Each node may also contain one or more scoreboards for managing the status of ongoing transactions. The internode cache coherence protocol implemented in the COUs may be used to detect and resolve communications errors, such as dropped message packets between nodes, late message delivery at a node, or node failure.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: PAUL N. LOEWENSTEIN, DAMIEN WALKER, PRIYAMBADA MITRA, ALI VAHIDSAFA, MATTHEW COHEN, JOSEPHUS EBERGEN, ANDREW BROCK
  • Publication number: 20190207714
    Abstract: A cache coherence system manages both internode and intranode cache coherence in a cluster of nodes. Each node in the cluster of nodes is either a collection of processors running an intranode coherence protocol between themselves, or a single processor. A node comprises a plurality of coherence ordering units (COUs) that are hardware circuits configured to manage intranode coherence of caches within the node and/or internode coherence with caches on other nodes in the cluster. Each node contains one or more directories which tracks the state of cache line entries managed by the particular node. Each node may also contain one or more scoreboards for managing the status of ongoing transactions. The internode cache coherence protocol implemented in the COUs may be used to detect and resolve communications errors, such as dropped message packets between nodes, late message delivery at a node, or node failure.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Applicant: Oracle International Corporation
    Inventors: PAUL N. LOEWENSTEIN, DAMIEN WALKER, PRIYAMBADA MITRA, ALI VAHIDSAFA, MATTHEW COHEN, JOSEPHUS EBERGEN, ANDREW BROCK