Patents by Inventor Prohor Chowdhury
Prohor Chowdhury has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9311274Abstract: A system includes a memory bank and a control unit. The control unit is configured to perform FFT computations based on Merged radix-2 butterfly calculations by performing FFT computations over N input items, and to access the memory bank for (½×log2N)×(10×log2N) times.Type: GrantFiled: October 17, 2013Date of Patent: April 12, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prohor Chowdhury, Alexander Tessarolo
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Publication number: 20150113030Abstract: A system includes a memory bank and a control unit. The control unit is configured to perform FFT computations based on Merged radix-2 butterfly calculations by performing FFT computations over N input items, and to access the memory bank for (½×log2 N)×(10×log2 N) times.Type: ApplicationFiled: October 17, 2013Publication date: April 23, 2015Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Prohor CHOWDHURY, Alexander TESSAROLO
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Patent number: 8943392Abstract: A decoding system suitable for Viterbi decoding includes a decoder that includes a state metrics array, a butterfly unit, and a constraint length multiplexer. The state metrics array includes registers in which each register is arranged to store a state metric for processing. The butterfly unit includes an array of butterfly elements where each butterfly element is arranged to generate intermediate state metrics in parallel with other butterfly elements in the butterfly unit. The constraint length multiplexer unit is arranged to generate new state metrics in response to the intermediate state metrics and a Viterbi constraint length value stored in a constraint length register. Transition bits can also be generated in response to the constraint length.Type: GrantFiled: November 6, 2012Date of Patent: January 27, 2015Assignee: Texas Instruments IncorporatedInventors: Prohor Chowdhury, Alexander Tessarolo
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Patent number: 8799713Abstract: A built-in self-test (BIST) diagnostic system tests the execution of a processor. The processor is arranged to execute a normal application for controlling a process that is external to the processor. The normal execution is executed in normal execution timeslots that have idle timeslots that are interspersed in time between the normal execution timeslots. A BIST controller is arranged to detect the presence of an idle timeslot in the execution of the processor and to use a scan chain to scan-in a first test pattern for a test application for testing the processor. The first test pattern is executed by the processor during the detected idle timeslot and a first result pattern generated by the execution of the first test pattern is scanned-out. The scanned-out first test pattern is evaluated to determine the presence of an error. The first test pattern application is conditionally interruptible.Type: GrantFiled: February 28, 2012Date of Patent: August 5, 2014Assignee: Texas Instruments IncorporatedInventors: Swathi Gangasani, Srinivasulu Alampally, Prohor Chowdhury, Srinivasa B S Chakravarthy, Padmini Sampath, Rubin Ajit Parekhji
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Patent number: 8739012Abstract: A co-hosted cyclical redundancy check (CRC) calculations system is arranged to use a processor to generate initial addresses for reading the data from a mirrored device that has address ranges over which a CRC result is to be calculated. An memory mapping unit detects when the initial address falls within an address range over which the CRC result is to be calculated. A read snoop unit snoops the data read from a mirrored memory that has data stored using a mirrored address. A CRC co-generator receives the snooped data read from mirrored memory and uses the snooped data read from the mirrored memory to calculate the CRC result.Type: GrantFiled: June 14, 2012Date of Patent: May 27, 2014Assignee: Texas Instruments IncorporatedInventors: Prohor Chowdhury, Alexander Tessarolo
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Publication number: 20140129908Abstract: A decoding system suitable for Viterbi decoding includes a decoder that includes a state metrics array, a butterfly unit, and a constraint length multiplexer. The state metrics array includes registers in which each register is arranged to store a state metric for processing. The butterfly unit includes an array of butterfly elements where each butterfly element is arranged to generate intermediate state metrics in parallel with other butterfly elements in the butterfly unit. The constraint length multiplexer unit is arranged to generate new state metrics in response to the intermediate state metrics and a Viterbi constraint length value stored in a constraint length register. Transition bits can also be generated in response to the constraint length.Type: ApplicationFiled: November 6, 2012Publication date: May 8, 2014Applicant: Texas Instruments, IncorporatedInventors: Prohor Chowdhury, Alexander Tessarolo
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Patent number: 8694878Abstract: Viterbi decoding is performed on a microcontroller by initializing a state-metric array by executing load instructions to load state-metric data from a memory module into a set of registers in the microcontroller. Butterfly processing on the state-metric array is performed by executing Viterbi processing instructions fetched from a program storage module to manipulate the state-metric (SM) data in the set of registers for each Viterbi butterfly in a stage of Viterbi decoding to form a final set of state-metric data and trace bits. After completing each stage, a final set of state-metric data is stored in the memory module by executing store instructions.Type: GrantFiled: June 13, 2012Date of Patent: April 8, 2014Assignee: Texas Instruments IncorporatedInventors: Prohor Chowdhury, Alexander Tessarolo
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Patent number: 8539602Abstract: Multiple secure environments are established within a system on a chip (SoC) by defining a first secure region within a non-volatile memory in the SoC with a first set of parameters written into a predefined parameter region of the non-volatile memory. A second secure region within the non-volatile memory may be defined at a later time by a second set of parameters written into another predefined parameter region of the non-volatile memory. A security module is initialized each time the SoC is powered on by transferring the first set of parameters and the second set of parameters from the parameter region to the security module in a manner that does not expose the first set of parameters or the second set of parameters to a program being executed by the processor. The multiple secure regions of the SoC are enforced by the security module according to the parameter data.Type: GrantFiled: June 20, 2012Date of Patent: September 17, 2013Assignee: Texas Instruments IncorporatedInventors: Prohor Chowdhury, Alexander Tessarolo, David Peter Foley
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Publication number: 20120331560Abstract: Multiple secure environments are established within a system on a chip (SoC) by defining a first secure region within a non-volatile memory in the SoC with a first set of parameters written into a predefined parameter region of the non-volatile memory. A second secure region within the non-volatile memory may be defined at a later time by a second set of parameters written into another predefined parameter region of the non-volatile memory. A security module is initialized each time the SoC is powered on by transferring the first set of parameters and the second set of parameters from the parameter region to the security module in a manner that does not expose the first set of parameters or the second set of parameters to a program being executed by the processor. The multiple secure regions of the SoC are enforced by the security module according to the parameter data.Type: ApplicationFiled: June 20, 2012Publication date: December 27, 2012Inventors: Prohor Chowdhury, Alexander Tessarolo, David Peter Foley
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Publication number: 20120324318Abstract: Viterbi decoding may be performed on a microcontroller by initializing a state-metric array by executing load instructions to load state-metric data from a memory module into a set of registers in the microcontroller. Butterfly processing on the state-metric array is performed by executing Viterbi processing instructions fetched from a program storage module to manipulate the state-metric (SM) data in the set of registers for each Viterbi butterfly in a stage of Viterbi decoding to form a final set of state-metric data and trace bits. After completing each stage, a final set of state-metric data may be stored in the memory module by executing store instructions.Type: ApplicationFiled: June 13, 2012Publication date: December 20, 2012Inventors: Prohor Chowdhury, Alexander Tessarolo
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Publication number: 20120324321Abstract: A co-hosted cyclical redundancy check (CRC) calculations system is arranged to use a processor to generate initial addresses for reading the data from a mirrored device that has address ranges over which a CRC result is to be calculated. An memory mapping unit detects when the initial address falls within an address range over which the CRC result is to be calculated. A read snoop unit snoops the data read from a mirrored memory that has data stored using a mirrored address. A CRC co-generator receives the snooped data read from mirrored memory and uses the snooped data read from the mirrored memory to calculate the CRC result.Type: ApplicationFiled: June 14, 2012Publication date: December 20, 2012Applicant: TEXAS INSTRUMENTS, INCORPORATEDInventors: Prohor Chowdhury, Alexander Tessarolo
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Publication number: 20120226942Abstract: A built-in self-test (BIST) diagnostic system tests the execution of a processor. The processor is arranged to execute a normal application for controlling a process that is external to the processor. The normal execution is executed in normal execution timeslots that have idle timeslots that are interspersed in time between the normal execution timeslots. A BIST controller is arranged to detect the presence of an idle timeslot in the execution of the processor and to use a scan chain to scan-in a first test pattern for a test application for testing the processor. The first test pattern is executed by the processor during the detected idle timeslot and a first result pattern generated by the execution of the first test pattern is scanned-out. The scanned-out first test pattern is evaluated to determine the presence of an error. The first test pattern application is conditionally interruptible.Type: ApplicationFiled: February 28, 2012Publication date: September 6, 2012Applicant: TEXAS INSTRUMENTS, INCORPORATEDInventors: Swathi Gangasani, Srinivasulu Alampally, Prohor Chowdhury, Srinivasa B S Chakravarthy, Padmini Sampath, Rubin Ajit Parekhji