Abstract: A liquid crystal display (LCD) and an operating method thereof are provided. The operating method includes the following steps. It is determined whether a first frame and a second frame following the first frame are dynamic frames. When the first frame and the second frame are dynamic frames, a timing controller of the LCD performs a polarity inversion on a polarity signal, so that the polarity signal corresponding to the first frame is the same as the polarity signal corresponding to the second frame. When the second frame is written into an LCD panel of the LCD, energy written into the LCD panel is reduced.

Abstract: A liquid crystal display (LCD) including a LCD panel having a plurality of pixels, a source driver outputting a plurality of pixel voltages to the LCD panel, a gate driver, and a timing controller is provided. During performing a polarity inversion on a polarity signal corresponding to a first frame, the timing controller sequentially outputs a first start signal and a second start signal to the gate driver in a first frame period corresponding to the first frame. The gate driver sequentially outputs a plurality of first scan signals and a plurality of second scan signals to the LCD panel according to the first start signal and the second start signal, so that the brightness corresponding to a plurality of gray levels in the first frame are equal to the brightness corresponding to the gray levels in a plurality of previous frames and a plurality of following frames.

Abstract: A liquid crystal display (LCD) and an operating method thereof are provided. The operating method includes the following steps. It is determined whether a first frame and a second frame following the first frame are dynamic frames. When the first frame and the second frame are dynamic frames, a timing controller of the LCD performs a polarity inversion on a polarity signal, so that the polarity signal corresponding to the first frame is the same as the polarity signal corresponding to the second frame. When the second frame is written into an LCD panel of the LCD, energy written into the LCD panel is reduced.

Abstract: A method and system of controlling halt and resumption of scanning actions of an LCD is disclosed. An incoming video source is monitored, and current scan line position and corresponding polarity are recorded. When an abnormal video source is detected, the LCD scanning is stopped at a halt scan line of a halt frame with a halt polarity. After a normal video source has been detected again, determination is made of a proper resumptive scan line and/or a resumptive polarity. The panel scanning is resumed at the resumptive scan line equal to the halt scan line and/or with the resumptive polarity matching the halt polarity.

Abstract: A method for initializing a memory device is provided. The method includes a step for transmitting at least N+1 clock cycles to the memory device, wherein the N is an amount of bits of output serial data of the memory device. During a clock cycle of the at least N+1 clock cycles, a first start/stop signal is transmitted to the memory device. During another clock cycle of the at least N+1 clock cycles, a second start/stop signal is transmitted to the memory device.

Abstract: A method for initializing a memory device is provided. The method includes a step for transmitting at least N+1 clock cycles to the memory device, wherein the N is an amount of bits of output serial data of the memory device. During a clock cycle of the at least N+1 clock cycles, a first start/stop signal is transmitted to the memory device. During another clock cycle of the at least N+1 clock cycles, a second start/stop signal is transmitted to the memory device.

Abstract: A system and method of controlling scanning actions of an LCD is disclosed. A timing controller (Tcon) output enable (OE) generator generates an original OE signal, and a noise detection unit generates a noise-detected signal upon detecting noise. An OE mask generator generates a mask signal according to the noise-detected signal and the original OE signal. A masking unit generates a resultant OE signal according to the mask signal and the original OE signal.

Abstract: A method and system of controlling halt and resumption of scanning actions of an LCD is disclosed. An incoming video source is monitored, and current scan line position and corresponding polarity are recorded. When an abnormal video source is detected, the LCD scanning is stopped at a halt scan line of a halt frame with a halt polarity. After a normal video source has been detected again, determination is made of a proper resumptive scan line and/or a resumptive polarity. The panel scanning is resumed at the resumptive scan line equal to the halt scan line and/or with the resumptive polarity matching the halt polarity.

Abstract: An automatic hold time fixing circuit unit includes a first switch having first and second ends connected to data input and output ports. An input end of a memory element is connected to the second end of the first switch. A second switch includes a first end connected to an output end of the memory element and a second end connected to the data output port. A control circuit includes first and second output terminals and first and second input terminals. The first and second output terminals are connected to control ends of the first and second switches. The first and second input terminals allow input of two clocks to the control circuit for controlling connection or disconnection of the first and second switches. The data stored in the memory element can be utilized to fix a hold time of the data, so that correct data can be obtained at the data output port.

Abstract: An automatic hold time fixing circuit unit includes a first switch having first and second ends connected to data input and output ports. An input end of a memory element is connected to the second end of the first switch. A second switch includes a first end connected to an output end of the memory element and a second end connected to the data output port. A control circuit includes first and second output terminals and first and second input terminals. The first and second output terminals are connected to control ends of the first and second switches. The first and second input terminals allow input of two clocks to the control circuit for controlling connection or disconnection of the first and second switches. The data stored in the memory element can be utilized to fix a hold time of the data, so that correct data can be obtained at the data output port.

Abstract: A split clock flip-flop (SC-SFF) includes a latch having a scan input terminal, a data input terminal, a clock input terminal and at least one output terminal for generating an output signal in response to a scan input signal received at the scan input terminal or a data input signal received at the data input terminal. The SC-SFF also includes a multiplexer having a scan clock input terminal, a functional clock input terminal and a clock output terminal, which is coupled with the clock input terminal of the latch, for providing the latch with either a scan clock received at the scan clock input terminal or a functional clock received at the functional input terminal, wherein the scan clock and the functional clock cause the latch to latch the scan input signal and the data input signal, respectively.