Abstract: A system may include a memory to store an enhancer to identify a branch instruction, having a miss-prediction rate above a threshold, in an executing thread. The system may additionally include an instruction update unit to modify an operation code (opcode) of the branch instruction, where a modified opcode of a branch instruction indicates an instruction fetch priority for an executing thread. The system may further include a processor, having an instruction decode unit to set a modified instruction fetch priority of the first executing thread based on the modified opcode of the branch instruction, and an instruction fetch unit to retrieve instructions for the first executing thread from the instruction cache at a first rate, the first rate indicated by the modified instruction fetch priority of the first executing thread.

Abstract: A computer system may determine a mode for a processor. The processor may support SMT, and it may have a first hardware thread with a first architected resource and a second hardware thread with a second architected resource. The computer system may determine that the processor is in a reduced-thread mode. The computer system may determine that the first hardware thread is a primary hardware thread that is active in the reduced-thread mode, and that the second hardware thread is a secondary hardware thread that is inactive in the reduced-thread mode. The computer system may disable the second hardware thread. The computer system may enable the first hardware thread to access the second architected resources.

Abstract: A system may include a memory to store an enhancer to identify a branch instruction, having a miss-prediction rate above a threshold, in an executing thread. The system may additionally include an instruction update unit to modify an operation code (opcode) of the branch instruction, where a modified opcode of a branch instruction indicates an instruction fetch priority for an executing thread. The system may further include a processor, having an instruction decode unit to set a modified instruction fetch priority of the first executing thread based on the modified opcode of the branch instruction, and an instruction fetch unit to retrieve instructions for the first executing thread from the instruction cache at a first rate, the first rate indicated by the modified instruction fetch priority of the first executing thread.

Abstract: A computer system may determine a mode for a processor. The processor may support SMT, and it may have a first hardware thread with a first architected resource and a second hardware thread with a second architected resource. The computer system may determine that the processor is in a reduced-thread mode. The computer system may determine that the first hardware thread is a primary hardware thread that is active in the reduced-thread mode, and that the second hardware thread is a secondary hardware thread that is inactive in the reduced-thread mode. The computer system may disable the second hardware thread. The computer system may enable the first hardware thread to access the second architected resources.