Abstract: A semiconductor structure with a back gate includes a device wafer includes a front side and a back side. A transistor is disposed on the front side, wherein the transistor includes a gate structure, a source and a drain. An interlayer dielectric covers the transistor. A first metal layer and a second metal layer are within the interlayer dielectric. A first conductive plug is within the interlayer dielectric and contacts the source and the first metal layer. A second conductive plug is disposed within the interlayer dielectric and contacts the drain and the second metal layer. A back gate, a source conductive pad and a drain conductive pad are disposed on the back side. A first via plug penetrates the device wafer to electrically connect the source conductive pad and the source. A second via plug penetrates the device wafer to electrically connect the drain conductive pad and the drain.

Abstract: A semiconductor structure including a substrate, a complementary metal oxide semiconductor (CMOS) device, a bipolar junction transistor (BJT), and a first interconnect structure is provided. The substrate has a first side and a second side opposite to each other. The CMOS device includes an NMOS transistor and a PMOS transistor disposed on the substrate. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the first side of the substrate. The emitter is disposed on the base. A top surface of a channel of the NMOS transistor, a top surface of a channel of the PMOS transistor and a top surface of the collector of the BJT have the same height. The first interconnect structure is electrically connected to the base at the first side of the substrate and extends to the second side of the substrate.

Abstract: A semiconductor structure including a substrate, a CMOS device and a BJT is provided. The substrate has a first side and a second side opposite to each other. The CMOS device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a first N-type doped region and a second N-type doped region disposed in the substrate. The PMOS transistor includes a first P-type doped region and a second P-type doped region disposed in the substrate. The BJT includes a collector, a base and an emitter. The base is disposed on the first side of the substrate. The emitter is disposed on the base. A first metal silicide layer, a second metal silicide layer, and a third metal silicide layer are respectively located on the second side of the substrate and respectively disposed on the collector, the first N-type doped region, and the first P-type doped region.

Abstract: A semiconductor structure including a substrate, a complementary metal oxide semiconductor (CMOS) device, a bipolar junction transistor (BJT), and a first protection layer is provided. The CMOS device includes an N-type metal oxide semiconductor (NMOS) transistor and a P-type metal oxide semiconductor (PMOS) transistor disposed on the substrate. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the substrate. The emitter is disposed on the base. A top surface of a channel of the NMOS transistor, a top surface of a channel of the PMOS transistor and a top surface of the collector of the BJT have the same height. The first protection layer is disposed on the substrate and exposes the substrate. The base is disposed on the substrate exposed by the first protection layer. The semiconductor structure can have better overall performance.

Abstract: A semiconductor structure with a high resistivity wafer includes a device wafer. The device wafer includes a front side and a back side. A semiconductor element is disposed on the front side. An interlayer dielectric covers the front side. A high resistivity wafer consists of an insulating material. A dielectric layer encapsulates the high resistivity wafer. The dielectric layer contacts the interlayer dielectric.

Abstract: A semiconductor device includes: a first gate line and a second gate line extending only along a first direction, a third gate line and a fourth gate line extending along the first direction and between the first gate line and the second gate line, a fifth gate line and a sixth gate line extending along a second direction between the first gate line and the second gate line and intersecting the third gate line and the fourth gate line, and first contact plugs on the first gate line. Preferably, the first direction is perpendicular to the second direction and the first gate line and the second gate line are directly connected to the fifth gate line and the sixth gate line.

Abstract: A semiconductor structure including a substrate, a complementary metal oxide semiconductor (CMOS) device and a bipolar junction transistor (BJT) is provided. The CMOS device includes an N-type metal oxide semiconductor (NMOS) transistor and a P-type metal oxide semiconductor (PMOS) transistor disposed on the substrate. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the substrate. The emitter is disposed on the base. A top surface of a channel of the NMOS transistor, a top surface of a channel of the PMOS transistor and a top surface of the collector of the BJT have the same height. The semiconductor structure can have better overall performance.

Abstract: A high resistivity wafer with a heat dissipation structure includes a high resistivity wafer and a metal structure. The high resistivity wafer includes a heat dissipation region and a device support region. The high resistivity wafer consists of an insulating material. The metal structure is only embedded within the heat dissipation region of the high resistivity wafer. The metal structure surrounds the device support region.

Abstract: A semiconductor structure with a high resistivity wafer includes a device wafer. The device wafer includes a front side and a back side. A semiconductor element is disposed on the front side. An interlayer dielectric covers the front side. A high resistivity wafer consists of an insulating material. A dielectric layer encapsulates the high resistivity wafer. The dielectric layer contacts the interlayer dielectric.

Abstract: A semiconductor device on silicon-on-insulator (SOI) substrate includes: a first gate line and a second gate line extending along a first direction, a third gate extending along a second direction and between the first gate line and the second gate line, and a drain region adjacent to one side of the third gate line. Preferably, the third gate line includes a first protrusion overlapping the drain region.

Abstract: A radiofrequency device includes a buried insulation layer, a transistor, a contact structure, a connection bump, an interlayer dielectric layer, and a mold compound layer. The buried insulation layer has a first side and a second side opposite to the first side in a thickness direction of the buried insulation layer. The transistor is disposed on the first side of the buried insulation layer. The contact structure penetrates the buried insulation layer and is electrically connected with the transistor. The connection bump is disposed on the second side of the buried insulation layer and electrically connected with the contact structure. The interlayer dielectric layer is disposed on the first side of the buried insulation layer and covers the transistor. The mold compound layer is disposed on the interlayer dielectric layer. The mold compound layer may be used to improve operation performance and reduce manufacturing cost of the radiofrequency device.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first silicon layer, an insulating layer on the first silicon layer, and a second silicon layer on the insulating layer; forming a metal-oxide semiconductor (MOS) transistor on the substrate; forming an interlayer dielectric layer (ILD) on the MOS transistor; removing part of the ILD layer to form a first trench to expose the insulating layer; and performing a wet etching process through the first trench to remove part of the insulating layer for forming a first air gap under the MOS transistor.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first silicon layer, an insulating layer on the first silicon layer, and a second silicon layer on the insulating layer; forming a metal-oxide semiconductor (MOS) transistor on the substrate; forming an interlayer dielectric layer (ILD) on the MOS transistor; removing part of the ILD layer to form a first trench to expose the insulating layer; and performing a wet etching process through the first trench to remove part of the insulating layer for forming a first air gap under the MOS transistor.

Abstract: A semiconductor structure including a substrate, a complementary metal oxide semiconductor (CMOS) device and a bipolar junction transistor (BJT) is provided. The CMOS device includes an N-type metal oxide semiconductor (NMOS) transistor and a P-type metal oxide semiconductor (PMOS) transistor disposed on the substrate. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the substrate. The emitter is disposed on the base. A top surface of a channel of the NMOS transistor, a top surface of a channel of the PMOS transistor and a top surface of the collector of the BJT have the same height. The semiconductor structure can have better overall performance.

Abstract: A method for fabricating semiconductor device comprising the steps of: forming a first trench and a second trench in a substrate; forming a liner in the first trench and the second trench; forming a first patterned mask on the substrate to cover the second trench; removing the liner in the first trench; removing the first patterned mask; and forming an insulating layer in the first trench and the second trench to form a trap rich isolation structure in the first trench and a deep trench isolation structure in the second trench.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.

Abstract: A method for fabricating semiconductor device comprising the steps of: forming a first trench and a second trench in a substrate; forming a liner in the first trench and the second trench; forming a first patterned mask on the substrate to cover the second trench; removing the liner in the first trench; removing the first patterned mask; and forming an insulating layer in the first trench and the second trench to form a trap rich isolation structure in the first trench and a deep trench isolation structure in the second trench.

Abstract: A method for forming a trench capacitor without an additional mask adder and the resulting device are provided. Embodiments include forming a buried implant layer over a substrate; forming an EPI layer over the buried implant layer; forming an oxide layer over the EPI layer; forming a nitride layer over the oxide layer; forming first and second trenches in the nitride layer, the oxide layer, the EPI layer, the buried implant layer and the substrate, the first trench being wider and deeper than the second trench; forming a dielectric layer in the trenches; forming a first polysilicon layer over the dielectric layer in the trenches; removing the first polysilicon layer and the dielectric layer above the EPI layer in the trenches and at a bottom of the first trench; and forming a second polysilicon layer filling the first trench and above the EPI layer in the second trench.

Abstract: A semiconductor structure including a substrate, a BJT, a first interconnect structure and a second interconnect structure is provided. The substrate has a first side and a second side opposite to each other. The BJT is located at the first side. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the substrate. The emitter is disposed on the base. The first interconnect structure is located at the first side and electrically connected to the base. The second interconnect structure is located at the second side and electrically connected to the collector. The first interconnect structure further extends to the second side. The first interconnect structure and the second interconnect structure are respectively electrically connected to an external circuit at the second side. The semiconductor structure can have better overall performance.

Abstract: A semiconductor device includes a buried insulation layer, a semiconductor layer, a gate structure, a source doped region, and a drain doped region. The semiconductor layer is disposed on the buried insulation layer. The gate structure is disposed on the semiconductor layer. The semiconductor layer includes a body region disposed between the gate structure and the buried insulation layer. The source doped region and the drain doped region are disposed in the semiconductor layer. A first contact structure penetrates the buried insulation layer and contacts the body region. A second contact structure penetrates the buried insulation layer and is electrically connected with the source doped region. At least a part of the first contact structure overlaps the body region in a thickness direction of the buried insulation layer. The body region is electrically connected with the source doped region via the first contact structure and the second contact structure.