Patents by Inventor Purnendu K. Mozumder
Purnendu K. Mozumder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7673262Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.Type: GrantFiled: May 13, 2008Date of Patent: March 2, 2010Assignee: PDF Solutions, Inc.Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
-
Publication number: 20080282210Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.Type: ApplicationFiled: May 13, 2008Publication date: November 13, 2008Applicant: PDF Solutions, Inc.Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
-
Patent number: 7373625Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.Type: GrantFiled: August 10, 2006Date of Patent: May 13, 2008Assignee: PDF Solutions, Inc.Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
-
Patent number: 7356800Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.Type: GrantFiled: August 10, 2006Date of Patent: April 8, 2008Assignee: PDF Solutions, Inc.Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
-
Patent number: 7174521Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.Type: GrantFiled: March 10, 2005Date of Patent: February 6, 2007Assignee: PDF Solutions, Inc.Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
-
Patent number: 6901564Abstract: A yield for an integrated circuit is predicted by processing a wafer to have a portion fabricated with at least one layout attribute of the integrated circuit. The portion of the wafer is analyzed to determine an actual yield associated with the at least one layout attribute. A systematic yield associated with the at least one layout attribute is determined based on the actual yield and a predicted yield associated with the at least one layout attribute. The predicted yield assumes that random defects are the only yield loss mechanism. A yield of an actual or proprosed product layout is predicted for the integrated circuit based on the systematic yield.Type: GrantFiled: July 18, 2002Date of Patent: May 31, 2005Assignee: PDF Solutions, Inc.Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
-
Publication number: 20030145292Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.Type: ApplicationFiled: July 18, 2002Publication date: July 31, 2003Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
-
Patent number: 6438439Abstract: A semiconductor processing tool evaluation and design method which replaces tool specifications with a requirements region plus associated evaluation functions for iterative feedback tool design.Type: GrantFiled: September 18, 1998Date of Patent: August 20, 2002Assignee: Texas Instruments IncorporatedInventors: Gabriel G. Barna, Joseph C. Davis, Purnendu K. Mozumder, Richard G. Burch
-
Patent number: 6388288Abstract: Integration of dual voltages on a single chip can be accomplished with a minimum of extra masks by optimizing only the MDD implant of the peripheral transistors, while other implants remain the same for both transistor types. This meets lifetime specifications without unnecessary expense.Type: GrantFiled: March 25, 1999Date of Patent: May 14, 2002Assignee: Texas Instruments IncorporatedInventors: Karthik Vasanth, Sharad Saxena, Richard G. Burch, Purnendu K. Mozumder, Joseph C. Davis, Chenjing L. Fernando, Suraj Rao
-
Patent number: 6381564Abstract: A method and system for providing optimal tuning for complex simulators. The method and system include initially building at least one RSM model having input and output terminals. Then there is provided a simulation-free optimization function by constructing an objective function from the outputs at the output terminals of the at least one RSM model and experimental data. The objective function is optimized in an optimizer and the optimized objective function is fed to the input terminal of the RSM. Building of at least one RSM model includes establishing a range for the simulation, running a simulation experiment for the designed experiment, extracting relevant data from said experiment and building the RSM model from the extracted relevant data. The step of running a simulation experiment comprises the step of running a DOE/Opt operation.Type: GrantFiled: May 3, 1999Date of Patent: April 30, 2002Assignee: Texas Instruments IncorporatedInventors: Joseph C. Davis, Karthik Vasanth, Sharad Saxena, Purnendu K. Mozumder, Suraj Rao, Chenjing L. Fernando, Richard G. Burch
-
Patent number: 6317640Abstract: Method for adequately modeling process induced variabilities is disclosed that comprises the steps of acquiring experimental data and defining a particular design space. Values for the mean and standard deviation of the experimental data at each of the points defining the design space are calculated. The experimental values of the output parameters at each of the design points is normalized to extract the shape of the distribution of each of the design points. The normalized values are then merged to form a cumulative distribution function associated with the data. The cumulative distribution function is applied to a new design point in a predicted fashion by first calculating a mean and standard deviation value for the new point by interpolating from the mean and standard deviation values from the experimental data. The cumulative distribution function is then scaled and centered using the interpolated mean and standard deviation values to provide a predicted data distribution for the new design point.Type: GrantFiled: January 5, 1999Date of Patent: November 13, 2001Assignee: Texas Instruments IncorporatedInventors: Suraj Rao, Sharad Saxena, Pushkar P. Apte, Purnendu K. Mozumder, Richard Gene Burch, Karthik Vasanth, Joseph Carl Davis, Chenjing L. Fernando
-
Patent number: 6311096Abstract: A statistical design method is provided for minimizing the impact of manufacturing variations on semiconductor manufacturing by statistical design which seeks to reduce the impact of variability on device behavior. The method is based upon a Markov representation of a process flow which captures the sequential and stochastic nature of semiconductor manufacturing and enables the separation of device and process models, statistical modeling of process modules from observable wafer states and approximations for statistical optimization over large design spaces. The statistical estimation component of this method results in extremely accurate predictions of the variability of transistor performance for all of the fabricated flows. Statistical optimization results in devices that achieve all transistor performance and reliability goals and reduces the variability of key transistor performances.Type: GrantFiled: April 1, 1999Date of Patent: October 30, 2001Assignee: Texas Instruments IncorporatedInventors: Sharad Saxena, Karthik Vasanth, Richard G. Burch, Purnendu K. Mozumder, Suraj Rao, Joseph C. Davis
-
Patent number: 6157062Abstract: A dual voltage chip is fabricated with no intermediate-doped (LDD or MDD) area in the high-voltage transistors by adjusting the gate sidewall spacer thickness and the source/drain implant.Type: GrantFiled: April 6, 1999Date of Patent: December 5, 2000Assignee: Texas Instruments IncorporatedInventors: Karthik Vasanth, Richard G. Burch, Sharad Saxena, Purnendu K. Mozumder, Chenjing L. Fernando, Joseph C. Davis, Suraj Rao
-
Patent number: 5912678Abstract: Methods and processes to reduce the cost and cycle time of designing manufacturing flows are described, particularly for microelectronic integrated circuit processes. One embodiment of the present invention is a method which divides the task of designing process flows into a number of abstraction levels and provides mechanisms to translate between these levels of abstraction. The process is divided into a number of modules each having process constraints. Process constraints are propagated backwards from the final module to the first module, and may also be propagated forward from earlier modules to later modules of needed. This approach results in a top-down design methodology where requirements from higher levels of abstraction are successively reduced to lower abstraction levels, while meeting the constraints imposed by the lower levels.Type: GrantFiled: April 14, 1997Date of Patent: June 15, 1999Assignee: Texas Instruments IncorporatedInventors: Sharad Saxena, Amy J. Unruh, Purnendu K. Mozumder, Richard G. Burch
-
Patent number: 5838595Abstract: The present invention configures a control strategy and a process model to calculate a setting of a machine. The present invention adjusts the process model in accordance with an analysis of the setting to control the machine.Type: GrantFiled: November 25, 1996Date of Patent: November 17, 1998Assignee: Texas Instruments, Inc.Inventors: Michael Francis Sullivan, Judith Susan Hirsch, Stephanie Watts Butler, Nicholas John Tovell, Jerry Alan Stefani, Purnendu K. Mozumder, Ulrich H. Wild, Chun-Jen Jason Wang, Robert A. Hartzell
-
Patent number: 5822241Abstract: A pass transistor for a 1-transistor dynammic random access memory (DRAM) integrated circuit with a square root relation between threshold adjustment dose and substrate bias.Type: GrantFiled: July 29, 1997Date of Patent: October 13, 1998Assignee: Texas Instruments IncorporatedInventors: Amitava Chatterjee, Purnendu K. Mozumder
-
Patent number: 5751582Abstract: A method is described for controlling a plurality of nonuniformity parameters in processing discrete products such as semiconductor wafers through a module consisting of several individual processes using site models. The method uses a controlled process to compensate for a subsequent uncontrolled process, which allows process goals of one process to be optimized to enhance the output of a subsequent process of the same module.Type: GrantFiled: September 24, 1996Date of Patent: May 12, 1998Assignee: Texas Instruments IncorporatedInventors: Sharad Saxena, Purnendu K. Mozumder, Gregory B. Shinn, Kelly J. Taylor
-
Patent number: 5546312Abstract: A method and system have been described for simultaneously controlling one or multiple metrics of non-uniformity using a model form independent multi-variable controller.Type: GrantFiled: February 24, 1994Date of Patent: August 13, 1996Assignee: Texas Instruments IncorporatedInventors: Purnendu K. Mozumder, Sharad Saxena
-
Patent number: 5526293Abstract: A system (10) for run-to-run control of semiconductor wafer processing is provided. An input/output device (12) receives a desired quality characteristic for a particular semiconductor fabrication process. A generating circuit (22) uses a model to generate appropriate process parameters for a processing unit (20) and an expected quality characteristic. An adjusting circuit (16) functions to adjust process parameter inputs of the processing unit (20). In-situ sensor (18) functions to measure a quality characteristic of the process in the processing unit (20) on a real-time basis. A comparing circuit (24) functions to compare the measured quality characteristic with the expected quality characteristic. A model adjusting circuit (26) may adjust the model of the generating circuit (22) if the measured quality characteristic varies from the expected quality characteristic by more than a predetermined statistical amount.Type: GrantFiled: December 17, 1993Date of Patent: June 11, 1996Assignee: Texas Instruments Inc.Inventors: Purnendu K. Mozumder, Gabe G. Barna
-
Patent number: 5408405Abstract: A method and system for controlling a plurality of process control variables for processing discrete products is described.Type: GrantFiled: September 20, 1993Date of Patent: April 18, 1995Assignee: Texas Instruments IncorporatedInventors: Purnendu K. Mozumder, Sharad Saxena, William W. Pu