Abstract: A method of forming an integrated circuit, including first, positioning a semiconductor wafer in a processing chamber; second, exposing portions of the semiconductor wafer, including introducing a first amount of hydrogen into the processing chamber and introducing a first amount of oxygen into the processing chamber; and, third, introducing at least one of a second amount of hydrogen or a second amount of oxygen into the processing chamber, the second amount of hydrogen greater than zero and less than the first amount of hydrogen and the second amount of oxygen greater than zero and less than the first amount of oxygen.

Abstract: Described examples include a resistor having a substrate having a non-conductive surface and a patterned polysilicon layer on the non-conductive surface, the patterned polysilicon layer including polycrystalline silicon wherein at least 90% of the grains in the polycrystalline silicon are 30 nm or smaller. The resistor also has a first terminal in conductive contact with the patterned polysilicon layer and a second terminal in conductive contact with the polysilicon layer and spaced from the first contact.

Abstract: A system and method for growing fine grain polysilicon. In one example, the method of forming an integrated circuit includes forming a dielectric layer over a semiconductor substrate, and forming a polysilicon layer over the dielectric layer. The polysilicon layer is formed by a chemical vapor deposition process that includes providing a gas flow including disilane and hydrogen gas over the semiconductor substrate.

Abstract: A method of forming an integrated circuit that includes placing a semiconductor substrate in a process chamber at an initial temperature, wherein one or more trenches are located within the semiconductor substrate. The temperature of the substrate is increased in a substantially oxygen-free ambient to an oxide-growth temperature. The temperature is then maintained at the oxide growth temperature while providing an oxidizing ambient, thereby forming an oxide layer on sidewalls of the trench. The temperature of the semiconductor wafer is then reduced to a final temperature below the initial temperature and removed from the process chamber.

Abstract: A microelectronic device including an analog MOS transistor. The analog transistor has a body well having a first conductivity type in a semiconductor material of a substrate of the microelectronic device. The body well extends deeper in the substrate than a field relief dielectric layer at the top surface of the semiconductor material. The analog transistor has a drain well and a source well having a second, opposite, conductivity type in the semiconductor material, both contacting the body well. The drain well and the source well extend deeper in the substrate than the field relief dielectric layer. The analog transistor has a gate on a gate dielectric layer over the body well. The drain well and the source well extend partway under the gate at the top surface of the semiconductor material.

Abstract: Described examples include an integrated circuit having a transistor with a first gate on a first gate insulating layer. The transistor also has second gate separated from the first gate by a gate gap. The integrated circuit also includes a channel well at the gate gap extending under the first gate and the second gate. The transistor has a first source in the channel adjacent to an edge of the first gate. The transistor having a second source formed in the channel adjacent to an edge of the second gate separated from the first source by a channel gap. The transistor has at least one back-gate contact, the at least one back-gate contact separated from the first gate by a first back-gate contact gap and separated from the second gate by a second back-gate contact gap.

Abstract: Apparatus, and their methods of manufacture, that include an insulating feature above a substrate and a resistor formed on the insulating feature. Forming the resistor includes depositing polysilicon and doping the polysilicon (e.g., in-situ) with a carbon dopant and/or an oxygen dopant.

Abstract: An integrated circuit (IC) includes a semiconductor surface layer of a substrate including circuitry formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal (MIM) capacitor. A multi-layer metal stack on the semiconductor surface layer includes a bottom plate contact metal layer including a bottom capacitor plate contact. A first interlevel dielectric (ILD) layer is over the bottom plate contact metal layer. The MIM capacitor includes a trench in the first ILD layer over the bottom capacitor plate contact, wherein the trench is lined by a bottom capacitor plate with a capacitor dielectric layer thereon, and a top capacitor plate on the capacitor dielectric layer. A fill material fills the trench to form a filled trench. A second ILD layer is over the filled trench. A filled via through the second ILD layer provides a connection to the top capacitor plate.

Abstract: A method of forming an integrated circuit, including first, positioning a semiconductor wafer in a processing chamber; second, exposing portions of the semiconductor wafer, including introducing a first amount of hydrogen into the processing chamber and introducing a first amount of oxygen into the processing chamber; and, third, introducing at least one of a second amount of hydrogen or a second amount of oxygen into the processing chamber, the second amount of hydrogen greater than zero and less than the first amount of hydrogen and the second amount of oxygen greater than zero and less than the first amount of oxygen.

Abstract: An integrated circuit includes a dielectric isolation structure formed at a surface of a semiconductor substrate and a polysilicon resistor body formed on the dielectric isolation structure. The polysilicon resistor body includes an N-type dopant having an N-type dopant concentration, nitrogen having a nitrogen concentration, and carbon having a carbon concentration. The sheet resistance of the resistor body is greater than 5 k?/square.

Abstract: Described examples include a resistor having a substrate having a non-conductive surface and a patterned polysilicon layer on the non-conductive surface, the patterned polysilicon layer including polycrystalline silicon wherein at least 90% of the grains in the polycrystalline silicon are 30 nm or smaller. The resistor also has a first terminal in conductive contact with the patterned polysilicon layer and a second terminal in conductive contact with the polysilicon layer and spaced from the first contact.

Abstract: A method of fabricating an IC includes providing a substrate including a semiconductor surface having well diffusions for a plurality of devices including bipolar, complementary metal oxide semiconductor (CMOS), and double-diffused MOS (DMOS) devices. A polysilicon layer is deposited on a dielectric layer over the semiconductor surface, an anti-reflective coating (ARC) layer is formed on the polysilicon layer, and a photoresist pattern is formed on the ARC layer. The ARC layer is etched in areas exposed by the photoresist pattern to define areas including gate areas having the ARC layer on the polysilicon layer. The photoresist pattern is removed. Polysilicon etching is performed in areas lacking the ARC layer to form polysilicon gates having a remaining ARC portion of the ARC layer thereon. A self-aligned ion implant uses the remaining ARC portion as an additional implant blocking layer for the polysilicon gates, and the remaining ARC portion is stripped.

Abstract: An integrated circuit (IC) includes a semiconductor surface layer of a substrate including circuitry formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal (MIM) capacitor. A multi-layer metal stack on the semiconductor surface layer includes a bottom plate contact metal layer including a bottom capacitor plate contact. A first interlevel dielectric (ILD) layer is over the bottom plate contact metal layer. The MIM capacitor includes a trench in the first ILD layer over the bottom capacitor plate contact, wherein the trench is lined by a bottom capacitor plate with a capacitor dielectric layer thereon, and a top capacitor plate on the capacitor dielectric layer. A fill material fills the trench to form a filled trench. A second ILD layer is over the filled trench. A filled via through the second ILD layer provides a connection to the top capacitor plate.

Abstract: A laterally diffused metal oxide silicon (LDMOS) transistor and a method of making the LDMOS transistor are disclosed. The LDMOS transistor includes a drain drift region formed in a substrate and containing a drain contact region. A gate structure overlies a channel region in the substrate and a first shallow-trench isolation (STI) structure located between the drain contact region and the channel region. The first STI structure contains a high-k dielectric and a second STI structure contains silicon oxide.

Abstract: An integrated circuit (IC) includes a semiconductor surface layer of a substrate including circuitry formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal (MIM) capacitor. A multi-layer metal stack on the semiconductor surface layer includes a bottom plate contact metal layer including a bottom capacitor plate contact. A first interlevel dielectric (ILD) layer is over the bottom plate contact metal layer. The MIM capacitor includes a trench in the first ILD layer over the bottom capacitor plate contact, wherein the trench is lined by a bottom capacitor plate with a capacitor dielectric layer thereon, and a top capacitor plate on the capacitor dielectric layer. A fill material fills the trench to form a filled trench. A second ILD layer is over including the filled trench. A filled via through the second ILD layer provides a contact to a top plate contact on the top capacitor plate.

Abstract: An integrated circuit (IC) includes a semiconductor surface layer of a substrate including circuitry formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal (MIM) capacitor. A multi-layer metal stack on the semiconductor surface layer includes a bottom plate contact metal layer including a bottom capacitor plate contact. A first interlevel dielectric (ILD) layer is over the bottom plate contact metal layer. The MIM capacitor includes a trench in the first ILD layer over the bottom capacitor plate contact, wherein the trench is lined by a bottom capacitor plate with a capacitor dielectric layer thereon, and a top capacitor plate on the capacitor dielectric layer. A fill material fills the trench to form a filled trench. A second ILD layer is over including the filled trench. A filled via through the second ILD layer provides a contact to a top plate contact on the top capacitor plate.

Abstract: A laterally diffused metal oxide silicon (LDMOS) transistor and a method of making the LDMOS transistor are disclosed. The LDMOS transistor includes a drain drift region formed in a substrate and containing a drain contact region. A gate structure overlies a channel region in the substrate and a first shallow-trench isolation (STI) structure located between the drain contact region and the channel region. The first STI structure contains a high-k dielectric and a second STI structure contains silicon oxide.

Abstract: A method of forming a semiconductor device includes forming source regions and drain regions in a semiconductor substrate, and a gate electrode over said semiconductor substrate and between said source and drain regions. The gate electrode is formed from a first semiconductor gate electrode layer deposited on said gate dielectric layer at a first substrate temperature. A second semiconductor gate electrode layer is deposited on the first semiconductor gate electrode layer at a second substrate temperature greater than said first temperature. The two gate electrode layers may be annealed to form a homogenous polycrystalline layer with improved grain size distribution, thereby improving transistor matching in a semiconductor device.

Abstract: A laterally diffused metal oxide silicon (LDMOS) transistor and a method of making the LDMOS transistor are disclosed. The LDMOS transistor includes a drain drift region formed in a substrate and containing a drain contact region. A gate structure overlies a channel region in the substrate and a first shallow-trench isolation (STI) structure is formed between the drain contact region and the channel region. The first STI structure contains a high-k dielectric and a second STI structure contains silicon dioxide.

Abstract: A method of forming a semiconductor device includes forming source regions and drain regions in a semiconductor substrate, and a gate electrode over said semiconductor substrate and between said source and drain regions. The gate electrode is formed from a first semiconductor gate electrode layer deposited on said gate dielectric layer at a first substrate temperature. A second semiconductor gate electrode layer is deposited on the first semiconductor gate electrode layer at a second substrate temperature greater than said first temperature. The two gate electrode layers may be annealed to form a homogenous polycrystalline layer with improved grain size distribution, thereby improving transistor matching in a semiconductor device.