Patents by Inventor Qi Xiang
Qi Xiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140258960Abstract: An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system.Type: ApplicationFiled: March 11, 2013Publication date: September 11, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Navneet Jain, Yunfei Deng, Mahbub Rashed, David Doman, Qi Xiang, Jongwook Kye
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Patent number: 8804407Abstract: An IC that includes a memory cell and a pass gate coupled to the memory cell, where the pass gate includes a PMOS transistor, is described. In one implementation, the PMOS transistor has a negative threshold voltage. In one implementation, the memory cell includes thick oxide transistors.Type: GrantFiled: July 12, 2011Date of Patent: August 12, 2014Assignee: Altera CorporationInventors: Jun Liu, Albert Ratnakumar, Irfan Rahim, Qi Xiang
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Patent number: 8750026Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.Type: GrantFiled: June 20, 2013Date of Patent: June 10, 2014Assignee: Altera CorporationInventors: Jun Liu, Yanzhong Xu, Shankar Sinha, Shih-Lin S. Lee, Jeffrey Xiaoqi Tung, Albert Ratnakumar, Qi Xiang, Irfan Rahim, Andy L. Lee, Jeffrey T. Watt, Srinivas Perisetty
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Patent number: 8735983Abstract: Metal-oxide-semiconductor transistors are provided. A metal-oxide-semiconductor transistor may be formed on a semiconductor substrate. Source and drain regions may be formed in the substrate. A gate insulator such as a high-K dielectric may be formed between the source and drain regions. A gate may be formed from multiple gate conductors. The gate conductors may be metals with different workfunctions. A first of the gate conductors may form a pair of edge gate conductors that are adjacent to dielectric spacers. An opening between the edge gate conductors may be filled with the second gate conductor to form a center gate conductor. A self-aligned gate formation process may be used in fabricating the metal-oxide-semiconductor transistor.Type: GrantFiled: November 26, 2008Date of Patent: May 27, 2014Assignee: Altera CorporationInventors: Jun Liu, Albert Ratnakumar, Qi Xiang, Jeffrey Xiaoqi Tung
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Patent number: 8735050Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. One method includes creating a master pattern layout including first and second adjacent cells. The first adjacent cell has a first border pin with a first routing line. The second adjacent cell has a second border pin with a second routing line. The first and second routing lines overlap to define an edge-edge stitch to couple the first and second border pins. The master pattern layout is decomposed into sub-patterns.Type: GrantFiled: August 6, 2012Date of Patent: May 27, 2014Assignee: GLOBALFOUNDRIES, Inc.Inventors: Lei Yuan, Hidekazu Yoshida, Jongwook Kye, Qi Xiang, Mahbub Rashed
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Patent number: 8649209Abstract: Integrated circuits with memory circuitry are provided. The memory circuitry may include memory cell transistors and associated pass transistors. The memory cell transistors and the pass transistors may be formed using multiple strips of oxide definition (OD) regions coupled in parallel. The multiple OD strips may have reduced widths. The ratio of the distance from adjacent OD strips to a given OD strip to the width of the given OD strip may be at least 0.5. Forming memory circuitry transistors using this multi-strip arrangement may provide increased levels of stress that improve transistor performance. Each OD strip may have a reduced width that still satisfies fabrication design rules. Forming OD regions having reduced width allows the pass transistors to be overdriven at higher voltage levels to further improve transistor performance.Type: GrantFiled: March 25, 2011Date of Patent: February 11, 2014Assignee: Altera CorporationInventors: Jun Liu, Qi Xiang
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Publication number: 20140035151Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. One method includes creating a master pattern layout including first and second adjacent cells. The first adjacent cell has a first border pin with a first routing line. The second adjacent cell has a second border pin with a second routing line. The first and second routing lines overlap to define an edge-edge stitch to couple the first and second border pins. The master pattern layout is decomposed into sub-patterns.Type: ApplicationFiled: August 6, 2012Publication date: February 6, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Lei Yuan, Hidekazu Yoshida, Jongwook Kye, Qi Xiang, Mahbub Rashed
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Patent number: 8633731Abstract: Integrated circuits such as programmable integrated circuits may have configuration random-access memory elements. The configuration random-access memory elements may be loaded with configuration data to customize programmable circuitry on the integrated circuits. Each memory element may have a bistable element that is powered using a positive power supply voltage and a negative power supply voltage. Programmable transistors in the programmable circuitry may have gates coupled to outputs of the bistable elements. The programmable transistors may have gate insulators that are thinner than gate insulators in the transistors of the bistable elements and may have threshold voltages of about zero volts. During operation, some of the configuration random-access memory elements may supply negative voltages to their associated programmable transistors so that the programmable transistors are provided with gate-source voltages of less than zero volts.Type: GrantFiled: August 9, 2011Date of Patent: January 21, 2014Assignee: Altera CorporationInventors: Irfan Rahim, Mao Du, Jeffrey Xiaoqi Tung, Jun Liu, Qi Xiang
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Patent number: 8530976Abstract: Integrated circuits may be provided that include memory elements that produce output control signals and corresponding programmable logic circuitry that receives the output control signals from the memory elements. The memory elements may include bistable storage elements formed from circuits such as cross-coupled inverters. The inverters may include n-channel metal-oxide-semiconductor transistors with p-metal gate conductors and n-channel metal-oxide-semiconductor transistors with p-metal gate conductors. These gate conductor assignments are the reverse of the gate conductor assignments used in the n-channel and p-channel transistors in other circuitry such as the programmable logic circuitry. The reversed gate conductor assignments increase the threshold voltages of the transistors in the memory elements to improve reliability in scenarios in which the memory elements are overdriving pass transistors in the programmable logic circuitry.Type: GrantFiled: May 23, 2011Date of Patent: September 10, 2013Assignee: Altera CorporationInventors: Albert Ratnakumar, Qi Xiang, Jun Liu
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Patent number: 8502283Abstract: A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.Type: GrantFiled: October 29, 2007Date of Patent: August 6, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Qi Xiang, Niraj Subba, Witold P. Maszara, Zoran Krivokapic, Ming-Ren Lin
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Patent number: 8482963Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.Type: GrantFiled: December 2, 2009Date of Patent: July 9, 2013Assignee: Altera CorporationInventors: Jun Liu, Yanzhong Xu, Shankar Sinha, Shih-Lin S. Lee, Jeffrey Xiaoqi Tung, Albert Ratnakumar, Qi Xiang, Irfan Rahim, Andy L. Lee, Jeffrey T. Watt, Srinivas Perisetty
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Publication number: 20120235662Abstract: A low-voltage reference circuit may have a pair of semiconductor devices. Each semiconductor device may have an n-type semiconductor region, an n+ region in the n-type semiconductor region, a metal gate, and a gate insulator interposed between the metal gate and the n-type semiconductor region through which carriers tunnel. The metal gate may have a work function matching that of p-type polysilicon. The gate insulator may have a thickness of less than about 25 angstroms. The metal gate may form a first terminal for the semiconductor device and the n+ region and n-type semiconductor region may form a second terminal for the semiconductor device. The second terminals may be coupled to ground. A biasing circuit may use the first terminals to supply different currents to the semiconductor devices and may provide a corresponding reference output voltage at a value that is less than one volt.Type: ApplicationFiled: March 18, 2011Publication date: September 20, 2012Inventors: Albert Ratnakumar, Qi Xiang, Simardeep Maangat, Jun Liu
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Patent number: 8264214Abstract: A low-voltage reference circuit may have a pair of semiconductor devices. Each semiconductor device may have an n-type semiconductor region, an n+ region in the n-type semiconductor region, a metal gate, and a gate insulator interposed between the metal gate and the n-type semiconductor region through which carriers tunnel. The metal gate may have a work function matching that of p-type polysilicon. The gate insulator may have a thickness of less than about 25 angstroms. The metal gate may form a first terminal for the semiconductor device and the n+ region and n-type semiconductor region may form a second terminal for the semiconductor device. The second terminals may be coupled to ground. A biasing circuit may use the first terminals to supply different currents to the semiconductor devices and may provide a corresponding reference output voltage at a value that is less than one volt.Type: GrantFiled: March 18, 2011Date of Patent: September 11, 2012Assignee: Altera CorporationInventors: Albert Ratnakumar, Qi Xiang, Simardeep Maangat, Jun Liu
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Patent number: 8242581Abstract: Mixed gate varactors are provided. The mixed gate varactors may include a semiconductor region of a given doping type. A first terminal for the varactor may be formed from a gate structure on the semiconductor region. A second terminal for the varactor may be formed from a heavily doped region in the semiconductor region that has the same doping type as the given doping type. A third terminal for the varactor may be formed from a heavily doped region in the semiconductor region that has a different doping type than the given doping type. The gate structure may include multiple gate conductors on a gate insulator. The gate insulator may be a high-K dielectric. The gate conductors may be metals or other materials that have different work functions. A conductive layer such as a layer of polysilicon may electrically connect the first and second gate conductors.Type: GrantFiled: November 26, 2008Date of Patent: August 14, 2012Assignee: Altera CorporationInventors: Albert Ratnakumar, Wilson Wong, Jun Liu, Qi Xiang, Jeffrey Xiaoqi Tung
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Patent number: 8218353Abstract: Integrated circuits with memory elements are provided. The memory elements may be arranged in a memory block. The memory block may include cross-coupled inverters that store data. The stored data may be used to program pass transistors. Transistors in the memory block may be stressed. Depending on the type of stress-inducing layer used, a tensile stress or a compressive stress may be built in into the transistors. Stressed transistors may help improve the routing speed of the memory block. Stressed transistors may be implemented using dual gate-oxide process.Type: GrantFiled: September 16, 2009Date of Patent: July 10, 2012Assignee: Altera CorporationInventors: Jun Liu, Shankar Sinha, Qi Xiang, Yow-Juang Liu
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Patent number: 8138791Abstract: Integrated circuits with stressed transistors are provided. Stressing transistors may increase transistor threshold voltage without the need to increase channel doping. Stressing transistors may reduce total leakage currents. It may be desirable to compressively stress N-channel metal-oxide-semiconductor (NMOS) transistors and tensilely stress P-channel metal-oxide-semiconductor (PMOS) transistors to reduce leakage currents. Techniques that can be used to alter the amount of stressed experienced by transistors may include forming a stress-inducing layer, forming a stress liner, forming diffusion active regions using silicon germanium, silicon carbon, or standard silicon, implementing transistors in single-finger instead of multi-finger configurations, and implanting particles. Any combination of these techniques may be used to provide appropriate amounts of stress to increase the performance or decrease the total leakage current of a transistor.Type: GrantFiled: January 27, 2010Date of Patent: March 20, 2012Assignee: Altera CorporationInventors: Albert Ratnakumar, Jun Liu, Jeffrey Xiaoqi Tung, Qi Xiang
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Patent number: 8081502Abstract: An integrated circuit with memory elements is provided. The memory elements may have memory element transistors with body terminals. Body bias control circuitry may supply body bias voltages that strengthen or weaken memory element transistors to improve read and write margins. The body bias control circuitry may dynamically control body bias voltages so that time-varying body bias voltages are supplied to memory element transistors. Address transistors and latch transistors in the memory elements may be selectively strengthened and weakened. Process variations may be compensated by weakening fast transistors and strengthening slow transistors with body bias adjustments.Type: GrantFiled: December 29, 2008Date of Patent: December 20, 2011Assignee: Altera CorporationInventors: Irfan Rahim, Jun Liu, Andy L. Lee, William Bradley Vest, Lu Zhou, Qi Xiang, Yanzhong Yu, Jeffrey Xiaoqi Tung, Albert Ratnakumar
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Patent number: 8059897Abstract: A method (400) for automatically performing a plurality of image processing functions on an electronic device (100) by providing a plurality of image processing option keys (405) including a first image processing option key and a second image processing option key. The first image processing option key is associated with a first image processing function and the second image processing option key is associated with a second image processing function that is different from the first image processing function. The method (400) performs capturing (410) a first image using a camera (119) in response to a user activation of the first image processing option key and then automatically performing (415) the first image processing function in response to capturing the first image.Type: GrantFiled: December 10, 2007Date of Patent: November 15, 2011Assignee: Motorola Mobility, Inc.Inventors: Xiang Xu, Qi Xiang Li, Zhao Hui Li, Ke Jiao Zhang
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Patent number: 7952423Abstract: A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit consisting plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source and the body terminal of the PMOS transistors are coupled a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors.Type: GrantFiled: September 30, 2008Date of Patent: May 31, 2011Assignee: Altera CorporationInventors: Qi Xiang, Albert Ratnakumar, Jeffrey Xiaoqi Tung, Weiqi Ding
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Patent number: 7923785Abstract: According to one exemplary embodiment, a FET which is situated over a substrate, comprises a channel situated in the substrate. The FET further comprises a first gate dielectric situated over the channel, where the first gate dielectric has a first coefficient of thermal expansion. The FET further comprises a first gate electrode situated over the first gate dielectric, where the first gate electrode has a second coefficient of thermal expansion, and where the second coefficient of thermal expansion is different than the first coefficient of thermal expansion so as to cause an increase in carrier mobility in the FET. The second coefficient of thermal expansion may be greater that the first coefficient of thermal expansion, for example. The increase in carrier mobility may be caused by, for example, a tensile strain created in the channel.Type: GrantFiled: August 18, 2003Date of Patent: April 12, 2011Assignee: GLOBALFOUNDRIES Inc.Inventors: Qi Xiang, Boon-Yong Ang, Jung-Suk Goo