Patents by Inventor Qian Gang

Qian Gang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8339451
    Abstract: There is disclosed a method in a mobile communications device, wherein the method comprises displaying a main image, selecting an object in the main image, displaying a plurality of object images comprising the selected object, selecting a target object image from the plurality of object images, and displaying a target candidate image associated with the target object image.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: December 25, 2012
    Assignee: Nokia Corporation
    Inventors: Kong Qiao Wang, Qian Gang
  • Publication number: 20110105194
    Abstract: There is disclosed a method in a mobile communications device, wherein the method comprises displaying a main image, selecting an object in the main image, displaying a plurality of object images comprising the selected object, selecting a target object image from the plurality of object images, and displaying a target candidate image associated with the target object image.
    Type: Application
    Filed: June 27, 2008
    Publication date: May 5, 2011
    Applicant: NOKIA CORPORATION
    Inventors: Kong Qiao Wang, Qian Gang
  • Patent number: 6001706
    Abstract: A method was achieved for fabricating field oxide regions (shallow trench isolation) having raised portions which are self-aligned and extend over edges of device areas. This results in FETs with improved sub-threshold characteristics and lower sub-threshold leakage currents. The method consists of forming a pad oxide and depositing a doped polysilicon layer and a hard mask layer on a silicon substrate. Shallow trenches are etched through the hard mask, doped polysilicon layer and partially into the silicon substrate. A thermal oxidation is used to form a liner oxide in the trenches and to oxidize, at a higher oxidation rate, the sidewalls of the doped polysilicon layer to form an oxide over the edges of the device areas. A gap-fill oxide is deposited in the trenches and chemical mechanical polished (CMP) back to the polysilicon layer. The remaining polysilicon layer over the device areas is selectively removed to provide a field oxide having raised portions formed over the edges of the device areas.
    Type: Grant
    Filed: December 8, 1997
    Date of Patent: December 14, 1999
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Poh Suan Tan, Lap Chan, Qinghua Zhong, Qian Gang