Patents by Inventor Qian Niu

Qian Niu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11974482
    Abstract: A display substrate and related devices are provided. The display substrate includes a plurality of first sub-pixels, second sub-pixels and third sub-pixels. In a first direction, the first sub-pixels and the third sub-pixels are arranged alternately to form a plurality of first sub-pixel rows, the second sub-pixels form a plurality of second sub-pixel rows, the first sub-pixel rows and the second sub-pixel rows are arranged alternately in a second direction, connection lines of center points of two first sub-pixels and two third sub-pixels form a first virtual quadrilateral, the two first sub-pixels are located at two vertex angles of the first virtual quadrilateral which are opposite to each other, one second sub-pixel is located within the first virtual quadrilateral, and the first virtual quadrilateral includes two interior angles each being equal to 90° and two interior angles each being not equal to 90°.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: April 30, 2024
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qian Xu, Tong Niu, Yan Huang, Guomeng Zhang, Chang Luo, Jianpeng Wu, Peng Xu, Fengli Ji, Yi Zhang, Benlian Wang, Ming Hu
  • Patent number: 5144580
    Abstract: The very accurate quantization of charge transport or electron current is achieved within a heterostructure substrate by defining a quantum wire within the substrate and propagating a a.c. potential characterized by a travelling wave envelope along the length of the quantum wire. The travelling wave a.c. potential is applied to the length of the quantum wire by two opposing lateral gate arrays defined within the substrate. For each gate on the array is provided a corresponding gate on the opposing array which is offset in the direction of the current transport by a predetermined distance. A succeeding space is then provided in both arrays where there is no gate. An offset a.c. potential is then applied to the gate of one array, the offset gate of the opposing array and to the array as a whole through an overlying gate running the longitudinal length of the quantum, wire which gate applies a spatially independent a.c. potential along the length of the quantum wire.
    Type: Grant
    Filed: August 21, 1990
    Date of Patent: September 1, 1992
    Assignee: Regents of the University of California
    Inventors: Qian Niu, Klaus Ensslin