Patents by Inventor Qiang Yu

Qiang Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220416393
    Abstract: Waveguide interconnects for semiconductor packages are disclosed. An example semiconductor package includes a first semiconductor die, a second semiconductor die, and a substrate positioned between the first and second dies. The substrate includes a waveguide interconnect to provide a communication channel to carry an electromagnetic signal. The waveguide interconnect is defined by a plurality of through substrate vias (TSVs). The TSVs in a pattern around the at least the portion of the substrate to define a boundary of the communication channel.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Inventors: Georgios Dogiamis, Johanna Swan, Adel Elsherbini, Shawna Liff, Beomseok Choi, Qiang Yu
  • Publication number: 20220399294
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die-level interposer having a first surface and an opposing second surface; a first die coupled to the first surface of the die-level interposer by a first hybrid bonding region having a first pitch; a second die coupled to the second surface of the die-level interposer by a second hybrid bonding region having a second pitch different from the first pitch; and a third die coupled to the second surface of the die-level interposer by a third hybrid bonding region having a third pitch different from the first and second pitches.
    Type: Application
    Filed: June 14, 2021
    Publication date: December 15, 2022
    Applicant: Intel Corporation
    Inventors: Georgios Dogiamis, Qiang Yu, Adel A. Elsherbini, Shawna M. Liff
  • Publication number: 20220399249
    Abstract: An integrated circuit (IC) package may be fabricated having an interposer, one or more microfluidic channels through the interposer, a first IC chip attached to a first side of the interposer, and a second IC chip attached to a second side of the interposer, where the first side of the interposer includes first bond pads coupled to first bond pads of the first IC chip, and the second side of the interposer includes second bond pads coupled to first bond pads of the second IC chip. In an embodiment of the present description, a liquid cooled three-dimensional IC (3DIC) package may be formed with the IC package, where at least two IC devices may be stacked with a liquid cooled interposer. In a further embodiment, the liquid cooled 3DIC package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: June 14, 2021
    Publication date: December 15, 2022
    Applicant: Intel Corporation
    Inventors: Georgios Dogiamis, Qiang Yu, Feras Eid, Adel Elsherbini, Kimin Jun, Johanna Swan, Shawna Liff
  • Patent number: 11515424
    Abstract: Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: November 29, 2022
    Assignee: Intel Corporation
    Inventors: Said Rami, Hyung-Jin Lee, Saurabh Morarka, Guannan Liu, Qiang Yu, Bernhard Sell, Mark Armstrong
  • Patent number: 11487521
    Abstract: A system and method to translate source code in a source language executable in a source computing system to a target language executable in a target computing system. Source code in the source language is parsed to generate a corresponding parse tree containing at least one tree node and at least one leaf. During traversal of the parse tree, at least one mutation script is applied. The mutation script directs at least one of: generating a stream expression comprising at least one token corresponding to values of the at least one node and the at least one leaf of the parse tree; and formulating at least one text output containing a text pattern specified in the mutation script and/or values of the at least one token. Source code in the target language is outputted based on the at least one text output.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: November 1, 2022
    Assignee: Next Pathway Inc.
    Inventors: Vladimir Antonevich, Badih Schoueri, Qiang Yu
  • Patent number: 11450991
    Abstract: A connector housing includes an accommodation space defined by four walls and formed with an insertion port. The four walls include a first wall extending in a first plane and a second wall extending in a second plane perpendicular to the first plane, the first wall is connected with the second wall at a corner of the connector housing. A first positioning groove is disposed in an edge of the first wall proximate to the insertion port and a first positioning tooth is disposed on an edge of the second wall. The first positioning tooth extends in the first plane by vertically bending and engaging within the first positioning groove. The first positioning tooth and the first positioning groove have a first locking feature preventing the first positioning tooth from being disengaged from the first positioning groove in a direction perpendicular to the second plane.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: September 20, 2022
    Assignees: Tyco Electronics (Shanghai) Co. Ltd., Tyco Electronics (Zhuhai) Ltd.
    Inventors: Jikang Wei, Huiliang Luo, Shufeng Jia, Qiang Yu, Hongwen Yang, Hongqiang Han, Jiahui Chen
  • Publication number: 20220249043
    Abstract: The present disclosure relates to a C-arm. The C-arm may include a connection component, a driving component, a first support component, and a second support component. The first support component may be configured to support a radiation generator. The second support component may be configured to support a radiation detector. The first support component and the second support may be movably connected to the connection component. The driving component may be configured to drive a movement of the first support component relative to the connection component.
    Type: Application
    Filed: April 22, 2022
    Publication date: August 11, 2022
    Applicant: SHANGHAI UNITED IMAGING HEALTHCARE CO., LTD.
    Inventors: Wenqiang LIU, Qiang YU, Baojian WANG
  • Publication number: 20220249042
    Abstract: The present disclosure provides a gantry for an X-ray system. The gantry may include a base section, a lifting section, and a swing section. The base section may be configured to move. A first end of the lifting section may be connected to the base section. A first end of the swing section may be rotatably connected to a second end of the lifting section. A radiation assembly may be disposed on a second end of the swing section.
    Type: Application
    Filed: April 24, 2022
    Publication date: August 11, 2022
    Applicant: SHANGHAI UNITED IMAGING HEALTHCARE CO., LTD.
    Inventors: Qiang YU, He ZHU, Zhanqiang KONG, Wenqiang LIU, Zhenwei WANG
  • Publication number: 20220242092
    Abstract: This invention provides gypsum wallboards with a unique microstructure where the walls between voids are enhanced in thickness and strength to substantially improve the strength and handling properties of the wallboards. A method of making lightweight gypsum wallboards is also provided.
    Type: Application
    Filed: April 19, 2022
    Publication date: August 4, 2022
    Applicant: United States Gypsum Company
    Inventors: Qiang YU, Weixin D. SONG
  • Patent number: 11349258
    Abstract: A self-locking plug includes a main body, a plug bush seat arranged in the main body for positioning a plug bush, at least one locking tab, and a linkage. The self-locking plug further includes a key mechanism arranged in the main body. The key mechanism includes a pressing portion and a driving portion which are respectively arranged at two ends of the key mechanism. The driving portion is associated with one end of the linkage, and is configured to drive the linkage to reciprocate in an axial direction of the main body to switch the locking tab between a releasing state and a locking state.
    Type: Grant
    Filed: July 3, 2020
    Date of Patent: May 31, 2022
    Assignee: BEIJING TOP ELECTRIC CO., LTD.
    Inventors: Haiqing Lin, Qiang Yu, Yue Zhang
  • Patent number: 11338548
    Abstract: This invention provides gypsum wallboards with a unique microstructure where the walls between voids are enhanced in thickness and strength to substantially improve the strength and handling properties of the wallboards. A method of making lightweight gypsum wallboards is also provided.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: May 24, 2022
    Assignee: United States Gypsum Company
    Inventors: Qiang Yu, Weixin D. Song
  • Patent number: 11306028
    Abstract: This invention provides low dust low density gypsum wallboard products having high total core void volumes, corresponding to low densities in the range of about 10 to 30 pcf. The wallboards have a set gypsum core formed between two substantially parallel cover sheets, the set gypsum core preferably having a total void volume from about 80% to about 92%, and made from a slurry including stucco, pregelatinized starch, and a naphthalenesulfonate dispersant. The combination of the pregelatinized starch and the naphthalenesulfonate dispersant also provides a glue-like effect in binding the set gypsum crystals together. The wallboard formulation, along with small air bubble voids (and water voids) provides dust control during cutting, sawing, routing, snapping, nailing or screwing down, or drilling of the gypsum-containing products.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: April 19, 2022
    Assignee: United States Gypsum Company
    Inventors: Qiang Yu, Weixin D. Song
  • Patent number: 11242433
    Abstract: A solid-liquid separation device includes a kettle body, a piston, a stirrer, a separation plate having filtration pores, and a filtration mesh. The kettle body is hollow along an axial direction to form a chamber body. The separation plate is fitly installed in the chamber body, and divides the chamber body into a washing chamber and a draining chamber. The piston and the stirrer are fitly disposed in the washing chamber. The filtration mesh is attached on a side of the separation plate to cover the filtration pores. The kettle body is further provided with a feed inlet, a water inlet, a material outlet, and a liquid outlet. The feed inlet and material outlet are communicated with the washing chamber, and the water inlet and the liquid outlet are communicated with the draining chamber. The method includes the following steps: feeding, solid-liquid separation, washing, and material discharge.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: February 8, 2022
    Assignee: GUANGZHOU INSTITUTE OF ENERGY CONVERSION, ACADEMY OF SCIENCES
    Inventors: Wen Wang, Xinshu Zhuang, Xuesong Tan, Qiong Wang, Qiang Yu, Wei Qi, Zhongming Wang
  • Patent number: 11206037
    Abstract: The disclosure belongs to the field of integrated circuits, and is used for reducing an area overhead and a power consumption of a pipelined analog-to-digital converter. Each stage of the pipelined analog-to-digital converter according to the disclosure comprises an analogue-to-digital converter, a digital-to-analog converter, a subtractor and an amplifier. According to the disclosure, an amplification time of the pipelined ADC is used for extra quantization, and a number of bits of each ADC is reduced on the premise of not increasing a number of stages of the pipelined ADC, so that a scale of each circuit is greatly reduced, and the power consumption and the area overhead are reduced.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: December 21, 2021
    Assignee: CHENGDU HUAWEI ELECTRONIC TECHNOLOGY CO., LTD.
    Inventors: Qiang Yu, Yuanjun Cen, Jinda Yang
  • Publication number: 20210376849
    Abstract: The disclosure belongs to the field of integrated circuits, and is used for reducing an area overhead and a power consumption of a pipelined analog-to-digital converter. Each stage of the pipelined analog-to-digital converter according to the disclosure comprises an analogue-to-digital converter, a digital-to-analog converter, a subtractor and an amplifier. According to the disclosure, an amplification time of the pipelined ADC is used for extra quantization, and a number of bits of each ADC is reduced on the premise of not increasing a number of stages of the pipelined ADC, so that a scale of each circuit is greatly reduced, and the power consumption and the area overhead are reduced.
    Type: Application
    Filed: September 30, 2020
    Publication date: December 2, 2021
    Inventors: Qiang YU, Yuanjun CEN, Jinda YANG
  • Patent number: D944311
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: February 22, 2022
    Assignee: Shenzhen Shadow Crown Technology Co., Ltd
    Inventors: Feiyue Deng, Qiang Yu
  • Patent number: D947272
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: March 29, 2022
    Assignee: Shenzhen Shadow Crown Technology Co., Ltd
    Inventors: Feiyue Deng, Qiang Yu
  • Patent number: D948596
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: April 12, 2022
    Assignee: Shenzhen Shadow Crown Technology Co., Ltd
    Inventors: Feiyue Deng, Qiang Yu
  • Patent number: D955321
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: June 21, 2022
    Inventor: Ji Qiang Yu
  • Patent number: D960223
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: August 9, 2022
    Assignee: Shenzhen Shadow Crown Technology Co., Ltd
    Inventors: Feiyue Deng, Qiang Yu