Abstract: Certain aspects of the present disclosure provide a semiconductor capacitor. The semiconductor capacitor generally includes an insulative layer, and a semiconductor region disposed adjacent to a first side of the insulative layer. The semiconductor capacitor also includes a first non-insulative region disposed adjacent to a second side of the insulative layer. In certain aspects, the semiconductor region may include a second non-insulative region, wherein the semiconductor region includes at least two regions having at least one of different doping concentrations or different doping types, and wherein one or more junctions between the at least two regions are disposed above or below the first non-insulative region.

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device and techniques for fabricating a semiconductor device. In certain aspects, the semiconductor device includes a fin, a first non-insulative region disposed adjacent to a first side of the fin, and a second non-insulative region disposed adjacent to a second side of the fin. In certain aspects, the first non-insulative region and the second non-insulative region are separated by a trench, at least a portion of the trench being filled with a dielectric material disposed around the fin.

Abstract: Semiconductor devices and methods of manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate; forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming a shielding spacer on a sidewall of the second shielding layer; forming the other of the source and drain regions with the second shielding layer and the shielding spacer as a mask; removing at least a portion of the shielding spacer; and forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of the second shielding layer or a possible remaining portion of the shielding spacer.

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor variable capacitor, and techniques for fabricating the same, implemented using a threshold voltage implant region. For example, the semiconductor variable capacitor generally includes a first non-insulative region disposed above a first semiconductor region, a second non-insulative region disposed above the first semiconductor region, and a threshold voltage (Vt) implant region interposed between the first non-insulative region and the first semiconductor region and disposed adjacent to the second non-insulative region. In certain aspects, the semiconductor variable capacitor also includes a control region disposed above the first semiconductor region such that a capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.

Abstract: The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate, and a semiconductor layer on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; and a channel region in the semiconductor layer and located between the source region and the drain region, wherein the MOSFET further comprises a back gate which is located in the semiconductor substrate and has a first doped region as a lower portion of the back gate and a second doped region as an upper portion of the back gate, and the second doped region of the back gate is self-aligned with the gate stack. The MOSFET can adjust a threshold voltage by changing doping type and doping concentration of the back gate.

Abstract: Certain aspects of the present disclosure provide a semiconductor variable capacitor. The semiconductor variable capacitor generally includes a first non-insulative region disposed above a semiconductor region, and a second non-insulative region disposed adjacent to the semiconductor region. In certain aspects, the semiconductor variable capacitor also includes a first silicide layer disposed above the second non-insulative region, wherein the first silicide layer overlaps at least a portion of the semiconductor region. In certain aspects, a control region may be disposed adjacent to the semiconductor region such that a capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.

Abstract: A semiconductor device and a method of manufacturing the same are provided, wherein an example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second semiconductor layer and the first semiconductor layer to form a fin; forming an isolation layer on the substrate, wherein the isolation layer exposes a portion of the first semiconductor layer; forming a sacrificial gate stack crossing over the fin on the isolation layer; selectively etching the second semiconductor layer with the sacrificial gate stack as a mask, to expose the first semiconductor layer; selectively etching the first semiconductor layer, to form a void beneath the second semiconductor layer; filling the void with a dielectric material; forming a third semiconductor layer on the substrate, to form source/drain regions; and forming a gate stack to replace the sacrificial gate stack.

Abstract: Certain aspects of the present disclosure provide a semiconductor capacitor. The semiconductor capacitor generally includes a first non-insulative region disposed above an insulative layer, an insulative region, and a second non-insulative region disposed adjacent to the insulative region, wherein the insulative layer is disposed above the second non-insulative region and the insulative region. In some cases, at least a portion of the insulative region is disposed above one or more portions of the second non-insulative region.

Abstract: There is disclosed a method for manufacturing a semiconductor device comprising two opposite types of MOSFETs formed on one semiconductor substrate, the method comprising: forming a portion of the MOSFET on the semiconductor substrate, said portion of said MOSFET comprising source/drains regions located in the semiconductor substrate, a dummy gate stack located between the source/drain region and above the semiconductor substrate and a gate spacer surrounding the dummy gate stack; removing the dummy gate stack of said MOSFET to form a gate opening which exposes the surface of the semiconductor substrate; forming an interfacial oxide layer on the exposed surface of the semiconductor structure; forming a high-K gate dielectric on the interfacial oxide layer within the gate opening; forming a first metal gate layer on the high-K gate dielectric; implanting doping ions in the first metal gate layer; forming a second metal gate layer on the first metal gate layer to fill up the gate opening; and annealing to diffu

Abstract: Certain aspects of the present disclosure provide a semiconductor variable capacitor. The semiconductor variable capacitor generally includes a first non-insulative region disposed above a semiconductor region, and a second non-insulative region disposed adjacent to the semiconductor region. In certain aspects, the semiconductor variable capacitor also includes a first silicide layer disposed above the second non-insulative region, wherein the first silicide layer overlaps at least a portion of the semiconductor region. In certain aspects, a control region may be disposed adjacent to the semiconductor region such that a capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.

Abstract: The present invention provides a method of manufacturing a fin field effect transistor, comprising: providing an SOI substrate comprising a substrate layer (100), a BOX layer (120) and an SOI layer (130); forming a basic fin structure from an SOI layer; forming source/drain regions (110) on both sides of the basic fin structure; forming a fin structure between the source/drain regions (110) from a basic fin structure; and forming a gate stack across the fin structure. The method of manufacturing a fin field effect transistor provided in the present invention can integrate a high-k gate dielectric layer, a metal gate, and stressed source/drain regions into the fin field effect transistor to enhance the performance of the semiconductor device.

Abstract: Semiconductor devices and methods for manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask; removing a portion of the second shielding layer which is next to the other of the source and drain regions; forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer; and forming a stressed interlayer dielectric layer on the substrate.

Abstract: A semiconductor device structure is provided. The semiconductor device includes a semiconductor substrate, a first device, and a second device. Each of the first and second devices includes a gate extending in a first direction, source/drain regions respectively formed on opposite first and second sides of the gate, dielectric spacers formed respectively on outer sidewalls of the gate on the first side and the second side, and conductive spacers serving contacts to the source/drain regions and formed respectively on outer sidewalls of the respective gate spacers. A second direction from the source/drain region on the first side to the source/drain region on the second side crosses the first direction.

Abstract: A quasi-nanowire transistor and a method of manufacturing the same are provided, the quasi-nanowire transistor comprising: providing an SOI substrate comprising a substrate layer (100), a BOX layer (120) and an SOI layer (130); forming a basic fin structure on the SOI layer, the basic fin structure comprising at least one silicon/silicon-germanium stack; forming source/drain regions (110) on both sides of the basic fin structure; forming a quasi-nanowire fin from a basic fin structure and an SOI layer thereunder; and forming a gate stack across the quasi-nanowire fin. The method can effectively control gate length characteristics. A semiconductor structure formed by the above method is also provided.

Abstract: A semiconductor device structure and a method for fabricating the same. A method for fabricating semiconductor device structure includes forming gate lines on a semiconductor substrate; forming gate sidewall spacers surrounding the gate lines; forming respective source/drain regions in the semiconductor substrate and on either side of the respective gate lines; forming conductive sidewall spacers surrounding the gate sidewall spacers; and cutting off the gate lines, the gate sidewall spacers and the conductive sidewall spacers at predetermined positions, in which the cut gate lines are electrically isolated gates, and the cut conductive sidewall spacers are electrically isolated lower contacts. The method is applicable to the manufacture of contacts in integrated circuits.

Abstract: The present invention presents a method for manufacturing a semiconductor device structure as well as the semiconductor device structure. Said method comprises: providing a semiconductor substrate; forming a first insulating layer on the semiconductor substrate; forming a shallow trench isolation embedded in the first insulating layer and the semiconductor substrate; forming a channel region embedded in the semiconductor substrate; and forming a gate stack stripe on the channel region. Said method further comprises, before forming the channel region, performing a source/drain implantation on the semiconductor substrate. By means of forming the source/drain regions in a self-aligned manner before forming the channel region and the gate stack, said method achieves the advantageous effects of the replacement gate process without using a dummy gate, thereby simplifying the process and reducing the cost.

Abstract: The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being disposed on the semiconductor substrate, and the semiconductor layer being disposed on the buried insulating layer; a gate stack disposed on the semiconductor layer; a source region and a drain region embedded in the semiconductor layer and disposed on both sides of the gate stack; and a channel region embedded in the semiconductor layer and sandwiched between the source region and the drain region, wherein the MOSFET further comprises a back gate and a counter doped region, and wherein the back gate is embedded in the semiconductor substrate, the counter doped region is disposed under the channel region and embedded in the back gate, and the back gate has a doping type opposite to that of the counter doped region.

Abstract: The present invention provides a substrate structure, a semiconductor device, and a manufacturing method thereof. The substrate structure comprises: a semiconductor substrate; and a first isolation region, wherein the first isolation region comprises: a first trench extending through the semiconductor substrate; and a first dielectric layer filling the first trench. Due to the isolation region extending through the substrate, it is possible to make device structures on both surfaces of the substrate, so as to increase the utilization of the substrate and the integration degree of the devices.

Abstract: A FinFET and a method of manufacturing the same are disclosed. The method includes forming a semiconductor fin. The method further includes forming a first region, the first region being one of a source region and a drain region. The method further includes forming a sacrificial spacer. The method further includes forming a second region with the sacrificial spacer as a mask, the second region being the other one of the source region and the drain region. The method further includes removing the sacrificial spacer. The method further includes replacing the sacrificial spacer with a gate stack comprising a gate conductor and a gate dielectric that separates the gate conductor from the semiconductor fin.

Abstract: The present invention discloses a semiconductor structure and a method for manufacturing the same, which comprises providing a substrate, and forming a stress layer, a buried oxide layer, and an SOI layer on the substrate; forming a doped region of the stress layer arranged in a specific position in the stress layer; forming an oxide layer and a nitride layer on the SOI layer, and forming a first trench that etches the nitride layer, the oxide layer, the SOI layer, and the buried oxide layer, and stops on the upper surface of the stress layer, and exposes at least part of the doped region of the stress layer; forming a cavity by wet etching through the first trench to remove the doped region of the stress layer; forming a polycrystalline silicon region of the stress layer and a second trench by filling the cavity with polycrystalline silicon and etching back; forming an isolation region by filling the second trench.