Abstract: In a tower integrated by the heating and drying section and the cooling section, both sides of the heating and drying section housing are provided with an air inlet box and an air outlet box; the air inlet box is communicating with a heat exchanger and distribution pipes in the heating and drying section housing, the air outlet box is communicating with distribution pipes in the heating and drying section housing and a dust remover; both sides of the cooling section housing are provided with an air inlet box and an air outlet box; the air inlet box is communicating with a heat exchanger and distribution pipes in the cooling section housing; the air outlet box is communicating with distribution pipes in the cooling section housing and a dust remover. The integral device improves the heat exchange effect and preventing the polypropylene particles from aging.

Abstract: A lightweight, thermal insulation and temperature-adjusting modified polymer aerogel composite material and a preparation method thereof are provided. The composite material includes a heat insulation matrix with a topological and closed-cell foaming structure; And an enhanced thermal insulation low thermal conductivity element embedded in the bubble wall of the thermal insulation matrix, i.e. the non-porous part. Due to the special foaming process, the aerogel phase change thermal insulation composite material has a tiny closed-cell structure similar to that of aerogel materials, and aerogel particles and phase change microcapsules are added, so that the internal cell structure and porosity are further improved, and the aerogel phase change thermal insulation composite material has a certain phase change temperature regulation function and excellent thermal insulation performance.

Abstract: A method and apparatus for inspecting a wind turbine blade. The method includes: acquiring a sound signal generated by an impingement of wind on the wind turbine blade using a sound acquisition device; generating a frequency spectrogram corresponding to the sound signal; and obtaining a damage recognition result of the wind turbine blade from the frequency spectrogram by performing image recognition on the frequency spectrogram based on a damage recognition model. With the method, a damage type of the wind turbine blade is accurately recognized based on the frequency spectrogram without manual inspection. Therefore, human resources are saved. In addition, the health state of the wind turbine blade can be monitored in real time.

Abstract: Disclosed is a method for processing an irradiation forecast. The method includes: acquiring irradiation forecast data corresponding to a target time period; calling a stacked generalization model including a first-layer generalizer and a second-layer generalizer; determining, using the first-layer generalizer, intermediate forecast data based on the irradiation forecast data corresponding to the target time period; and determining, using the second-layer generalizer, an output forecast value corresponding to the target time period based on the intermediate forecast data. In a technical solution according to an embodiment of the present disclosure, a method for processing an irradiation forecast is achieved.

Abstract: Disclosed are a method and apparatus for detecting a fault, and a method and apparatus for training a model. The method includes: acquiring characteristic data and actual temperature of a first wind turbine among n wind turbines, wherein the characteristic data of the first wind turbine is intended to characterize a working state of the first wind turbine, and n is an integer greater than 1; acquiring a prediction temperature set by inputting the characteristic data of the first wind turbine into a temperature prediction model corresponding to each of the n wind turbines; and detecting, based on the predicted temperature set and the actual temperature of the first wind turbine, whether the first wind turbine encounters a fault.

Abstract: Disclosed are a method and apparatus for detecting a yaw-to-wind abnormality. The method includes: acquiring a wind direction deviation angle within a specified time period; calculating a power performance index, wherein the power performance index is a dimensionless number used to characterize power generation performance of a wind turbine; determining an optimal wind direction deviation angle based on the power performance index; determining a current wind direction deviation angle according to probability distribution of the wind direction deviation angle; and if a difference between the optimal wind direction deviation angle and the current wind direction deviation angle is greater than a preset threshold, determining that a yaw-to-wind abnormality is detected.

Abstract: A method and apparatus for inspecting a wind turbine blade. The method includes: acquiring a sound signal generated by an impingement of wind on the wind turbine blade using a sound acquisition device; generating a frequency spectrogram corresponding to the sound signal; and obtaining a damage recognition result of the wind turbine blade from the frequency spectrogram by performing image recognition on the frequency spectrogram based on a damage recognition model. With the method, a damage type of the wind turbine blade is accurately recognized based on the frequency spectrogram without manual inspection. Therefore, human resources are saved. In addition, the health state of the wind turbine blade can be monitored in real time.

Abstract: Disclosed are a method and apparatus for detecting a yaw-to-wind abnormality. The method includes: acquiring a wind direction deviation angle within a specified time period; calculating a power performance index, wherein the power performance index is a dimensionless number used to characterize power generation performance of a wind turbine; determining an optimal wind direction deviation angle based on the power performance index; determining a current wind direction deviation angle according to probability distribution of the wind direction deviation angle; and if a difference between the optimal wind direction deviation angle and the current wind direction deviation angle is greater than a preset threshold, determining that a yaw-to-wind abnormality is detected.

Abstract: Disclosed are a method and apparatus for detecting a fault, and a method and apparatus for training a model. The method includes: acquiring characteristic data and actual temperature of a first wind turbine among n wind turbines, wherein the characteristic data of the first wind turbine is intended to characterize a working state of the first wind turbine, and n is an integer greater than 1; acquiring a prediction temperature set by inputting the characteristic data of the first wind turbine into a temperature prediction model corresponding to each of the n wind turbines; and detecting, based on the predicted temperature set and the actual temperature of the first wind turbine, whether the first wind turbine encounters a fault.

Abstract: The present disclosure relates to a method and apparatus for modeling a photovoltaic power curve, and a computer device and a storage medium thereof. The method includes: acquiring photovoltaic data at various time points within a specified time period; dividing the photovoltaic data at the various time points into at least two photovoltaic data packets; and establishing, according to the respective photovoltaic data of the at least two photovoltaic data packets, packet photovoltaic power curves respectively corresponding to the at least two photovoltaic data packets. By the method, the photovoltaic data is fitted in different time periods during the photovoltaic curve modeling process, thereby reducing the influence of the difference between photoelectric conversion efficiencies in different time periods on photovoltaic curve modeling, and improving the accuracy of photovoltaic curve modeling.

Abstract: Disclosed is a method for processing an irradiation forecast. The method includes: acquiring irradiation forecast data corresponding to a target time period; calling a stacked generalization model including a first-layer generalizer and a second-layer generalizer; determining, using the first-layer generalizer, intermediate forecast data based on the irradiation forecast data corresponding to the target time period; and determining, using the second-layer generalizer, an output forecast value corresponding to the target time period based on the intermediate forecast data. In a technical solution according to an embodiment of the present disclosure, a method for processing an irradiation forecast is achieved.

Abstract: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate.

Abstract: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. The integrated circuit structure includes a semiconductor layer with a major surface and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. The integrated circuit includes a capacitor having a bottom plate, dielectric layer and a top plate. In an associated method of manufacture, a first device region, is formed on a semiconductor layer. A field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers and a dielectric layer is formed on the semiconductor layer.

Abstract: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate.

Abstract: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate.

Abstract: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. The integrated circuit structure includes a semiconductor layer with a major surface and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. The integrated circuit includes a capacitor having a bottom plate, dielectric layer and a top plate. In an associated method of manufacture, a first device region, is formed on a semiconductor layer. A field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers and a dielectric layer is formed on the semiconductor layer.

Abstract: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. The integrated circuit structure includes a semiconductor layer with a major surface and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. The integrated circuit includes a capacitor having a bottom plate, dielectric layer and a top plate. In an associated method of manufacture, a first device region. is formed on a semiconductor layer. A field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers and a dielectric layer is formed on the semiconductor layer.

Abstract: An architecture for creating a vertical silicon-on-insulator MOSFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain contact region formed in the surface. A relatively thin single crystalline layer is oriented vertically above the major surface and comprises a first source/drain doped region over which is located a doped channel region, over which is located a second source/drain region. An insulating layer is disposed adjacent said first and said second source/drain regions and said channel region, serving as the insulating material of the SOI device. In another embodiment, insulating material is adjacent only said first and said second source/drain regions. A conductive region is adjacent the channel region for connecting the back side of the channel region to ground, for example, to prevent the channel region from floating.

Abstract: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate.

Abstract: An architecture for creating a vertical silicon-on-insulator MOSFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain contact region formed in the surface. A relatively thin single crystalline layer is oriented vertically above the major surface and comprises a first source/drain doped region over which is located a doped channel region, over which is located a second source/drain region. An insulating layer is disposed adjacent said first and said second source/drain regions and said channel region, serving as the insulating material of the SOI device. In another embodiment, insulating material is adjacent only said first and said second source/drain regions. A conductive region is adjacent the channel region for connecting the back side of the channel region to ground, for example, to prevent the channel region from floating.